Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The substrate includes a plurality of protrusions spaced apart from each other, and one of the plurality of graphene nanoribbons is on the substrate and between two adjacent protrusions. An interdigital electrode is placed on the graphene nanoribbon composite structure, and the interdigital electrode covers the plurality of protrusions and is electrically connected to the plurality of graphene nanoribbons.

An etchant composition includes phosphoric acid and a silane compound represented by the following Chemical Formula 1:

##STR00001## wherein A is an n-valent radical, L is C.sub.1-C.sub.5 hydrocarbylene, R.sup.1 to R.sup.3 are independently hydrogen, hydroxy, hydrocarbyl, or alkoxy, in which R.sup.1 to R.sup.3 exist respectively or are connected to each other by a heteroelement, and n is an integer of 2 to 5.

Methods for fabricating a graphene nanoribbon array in accordance with several embodiments of the present invention can include the steps of depositing PMMA dots on a substrate in an mn grid, to selectively seed graphene flakes on the substrate by controlling the growth of the graphene flakes on the substrate during the graphene deposition. The methods can further include the steps of masking the graphene flake edges with an insulator layer, at a very low deposition time or at a lower precursor concentration, to ensure there are not enough insulator molecules to form a complete layer over the flakes, but only enough insulator to form around the flakes edges. Once the graphene flake edges are masked, the bulk graphene can be etched, and the masking insulator can be removed to expose the resulting graphene nanoribbon.

A method for patterning a piece of carbon nanomaterial. The method comprises generating a first light pulse sequence with first light pulse sequence property values, the first light pulse sequence comprising at least one light pulse and exposing a first area of the piece of carbon nanomaterial to said first light pulse sequence in a first process environment having a first oxygen content, without exposing at least part of the piece of carbon nanomaterial to said first light pulse sequence. In this way, the method comprises oxidizing locally, in the first area, at least some carbon atoms of the piece of carbon nanomaterial in such a way that at most 10% of the carbon atoms of the first area are removed from the first area; thereby patterning the first area of the piece of carbon nanomaterial. In addition a processed piece of carbon nanomaterial.

An etching method is provided for processing a substrate that includes a first region having an insulating film arranged on a silicon layer and a second region having the insulating film arranged on a metal layer. The etching method includes a first step of etching the insulating film into a predetermined pattern using a plasma generated from a first gas until the silicon layer and the metal layer are exposed, and a second step of further etching the silicon layer after the first step using a plasma generated from a second gas including a bromide-containing gas.

There is provided a method for implementing and regulating patterning of a graphene film by ultraviolet photo-oxidation, including: implementing patterning of a graphene film micron structure pattern by using a xenon lamp excimer ultraviolet photo-oxidation vacuum apparatus and a hard mask; 2: controlling oxygen excitons, by applying a non-uniform magnetic field on the surface of the graphene film in a vertical direction, to move toward the graphene film in a direction of a magnetic field, so as to enhance the directivity of etching to the graphene film in the vertical direction, thereby improving patterning quality of the graphene film with micron-structure; and (3) by adjusting the intensity and direction of the magnetic field moving direction of the oxygen excitons is controlled, and the shape of the etched pattern structure of the graphene film is controlled, and thus controlling the patterning of the graphene film may be achieved.

A method of catalyst-assisted chemical etching with a vapor-phase etchant has been developed. In one approach, a semiconductor substrate including a patterned titanium nitride layer thereon is heated, and an oxidant and an acid are evaporated to form a vapor-phase etchant comprising an oxidant vapor and an acid vapor. The semiconductor substrate and the patterned titanium nitride layer are exposed to the vapor-phase etchant during the heating of the semiconductor substrate. The vapor-phase etchant diffuses through the patterned titanium nitride layer, and titanium nitride-covered regions of the semiconductor substrate are etched. Thus, an etched semiconductor structure is formed.

A method of fabricating a graphene-based solid-state device, the method including: disposing a graphene layer on a substrate; depositing a sacrificial layer on the graphene layer, the sacrificial layer being made of a non-polymeric dielectric material; patterning the graphene layer by defining at least one channel region, wherein the patterning is done by applying a lithographic process followed by an etching process using a resist layer, thus obtaining a patterned graphene layer protected against contamination from the resist layer by the sacrificial layer; patterning on the graphene layer a geometry of at least one metallic contact to be deposited; depositing the metallic contact on the graphene layer. A graphene-based solid-state device includes: a substrate; a graphene layer disposed thereon and defining at least one graphene channel; the graphene layer protected by a sacrificial layer made of a non-polymeric dielectric material; at least one metallic contact in contact with the graphene channel.