There is provided a method for planarizing irregularities in a surface of a grapheme layer formed on a substrate, including: planarizing the grapheme layer by removing graphene constituting a convex portion in the surface of the grapheme layer by anisotropically etching the grapheme layer using a plasma etching in an in-plane direction from an edge portion of the graphene.

The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

In accordance with an example embodiment of the present invention, a device comprising one or more porous graphene layers, the or each graphene porous layer comprising a multiplicity of pores. The device may form at least part of a flexible and/or stretchable, and or transparent electronic device.

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same materialgraphene.

An etching method is provided for processing a substrate that includes a first region having an insulating film arranged on a silicon layer and a second region having the insulating film arranged on a metal layer. The etching method includes a first step of etching the insulating film into a predetermined pattern using a plasma generated from a first gas until the silicon layer and the metal layer are exposed, and a second step of further etching the silicon layer after the first step using a plasma generated from a second gas including a bromide-containing gas.

In an embodiment, a method for transferring a pattern constituted by vertical spacers arranged on a template with intervals to the template, includes depositing by plasma-enhanced cyclic deposition a layer as a spacer umbrella layer substantially only on a top surface of each vertical spacer made of silicon or metal oxide, wherein substantially no layer is deposited on sidewalls of the vertical spacers and on an exposed surface of the template, followed by transferring the pattern constituted by the vertical spacers to the template by anisotropic etching using the vertical spacers with the spacer umbrella layers.

A method of manufacturing a semiconductor device is provided. The method includes: grinding a surface of an SiC wafer so that a crushed layer having a thickness of 5 nm or more is formed in a range exposed on the surface; forming a metal layer covering the crushed layer; and making the metal layer and the crushed layer react with each other by heating so as to form a silicide layer in ohmic contact with the SiC wafer. At least a part of the crushed layer covered with the metal layer transforms to the silicide layer over its entire depth.

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same materialgraphene.

The invention provides a recess structure for print deposition process and manufacturing method thereof. By disposing the dam (2) enclosing the recess (3) as comprising at least two stacked branch dam layers, and increasing the contact angle between the inclined inner circumferential surface of recess (3) enclosed by the branch dam layers and ink in a layer-by-layer manner, to limit height the ink able to climb on the inclined inner circumferential surface of the recess (3), the invention can improve the thickness uniformity of the organic functional layers printed in the recess and the photoelectric properties of organic functional layers. The recess (3) fabricated by the manufacturing method can limit height the ink able to climb on inclined inner circumferential surface of the recess (3) to improve the thickness uniformity of the organic functional layers printed in the recess and the photoelectric properties of organic functional layers.

An active element array substrate includes a substrate, first to third data lines extending along a first direction, first and second scan lines and a common electrode line extending along a second direction, and first to third sub-pixel units that are provided on the substrate. The first and third data lines respectively intersect with first and second adjacent ones of the first scan lines to define a pixel region. The second data line is located between the first and third data lines and passes through the pixel region. The first data line intersects with the second scan line and the common electrode line to define a plurality of sub-pixel regions in the pixel region. The first to third sub-pixel units are respectively provided in the sub-pixel regions and respectively electrically connected to the first data line and the first one of the first scan lines, the second data line and the second scan line, and the third data line and the second scan line.