A manufacturing method of a touch panel includes the steps of providing a substrate, forming a first conductive film on the substrate, forming a first mask on the first conductive film, etching the first conductive film to form electrode portions and lower intersect portions of the touch panel, forming an insulating film made of a negative resist on the first conductive film, and forming a contact hole above the electrode portion by removing the insulating film. The steps further include forming a second conductive film on the insulating film, forming a second mask on the second conductive film, etching the second conductive film to form an upper intersect portion connected between two adjacent electrode portions via the contact hole and intersecting with the lower intersect portion, and forming protective film on the second conductive film.

A method of manufacturing a semiconductor element includes forming a first silicon oxide film on a semiconductor wafer under a first film forming condition; forming a second silicon oxide film on the first silicon oxide film under a second film forming condition, a density of the second silicon oxide film being lower than a density of the first silicon oxide film; coating, with a photoresist, a region including the second silicon oxide film; exposing the photoresist using a photomask having an aperture and being disposed such that at least a portion of an edge of the aperture is disposed on the second silicon oxide film; removing a portion of the photoresist to form a photoresist pattern that has an overhang shape in a cross-section of the photoresist pattern; forming an electrode film on a region including the photoresist pattern; and performing lift-off by removing the photoresist pattern.

Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.

A dielectric electrode assembly, and a method (600) of manufacture thereof, including: a dielectric tube (226) having a cylindrical cross-section and a relative dielectric constant, .sub.2, the dielectric tube (226) filled with a gas having a relative dielectric constant, .sub.1; a structural dielectric (225) having a relative dielectric constant, .sub.3 surrounding the dielectric tube (226); metal electrodes (224) on opposite sides of the structural dielectric (225), the metal electrodes (224) having a flat cross-sectional geometry; and the structural dielectric (225) made from a material selected such that the relative dielectric constants of the structural dielectric (225), the dielectric tube (226), and the gas are interrelated and an approximately uniform electric field is generated within the dielectric tube (226) when power is applied to the metal electrodes (224).

A system and method for fabricating at least one of, a molecular device element and a TBELMD including depositing a first electrode material on an insulating substrate or layer, performing a photolithography process in the first electrode material, creating a trench component in the first electrode material with the photolithography process, determining a section of the electrode material to remove based on at least one of, a molecular device element and a TBELMD to be produced, removing the section of said first electrode material, oxidizing a portion of the first electrode material, creating a first insulator part from the oxidized portion of the first electrode material, in which the oxidized portion of the first electrode material includes at least a first electrode metal surface, depositing a second electrode material, and bridging the first and second electrode material.

Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a diamond layer are sequentially deposited on the III-Nitride layer. Next, a substrate wafer that includes a glass substrate (or a silicon substrate covered by a protection layer) is glass bonded to the diamond layer. Then, the silicon carrier wafer and the protection layer are removed.

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a diamond layer are sequentially deposited on the III-Nitride layer. Next, a support wafer that includes a GaN layer (or a silicon layer covered by a protection layer) is deposited on the diamond layer. Then, the silicon carrier wafer and the protection layer are removed.

A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.

Methods for fabricating a graphene nanoribbon array in accordance with several embodiments of the present invention can include the steps of depositing PMMA dots on a substrate in an mn grid, to selectively seed graphene flakes on the substrate by controlling the growth of the graphene flakes on the substrate during the graphene deposition. The methods can further include the steps of masking the graphene flake edges with an insulator layer, at a very low deposition time or at a lower precursor concentration, to ensure there are not enough insulator molecules to form a complete layer over the flakes, but only enough insulator to form around the flakes edges. Once the graphene flake edges are masked, the bulk graphene can be etched, and the masking insulator can be removed to expose the resulting graphene nanoribbon.