H01L21/185

Simultaneous bonding approach for high quality wafer stacking applications

In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer.

Semiconductor device manufacturing method and semiconductor device
11101167 · 2021-08-24 · ·

A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; forming a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.

SUBSTRATE POSITIONING APPARATUS, SUBSTRATE POSITIONING METHOD, AND BONDING APPARATUS
20210249293 · 2021-08-12 ·

A substrate positioning apparatus includes a holder and a rotating device. The holder is configured to hold a substrate. The rotating device is configured to rotate the holder. The rotating device includes a rotation shaft, a bearing member, a base member, a driving unit and a damping device. The rotation shaft is fixed to the holder. The bearing member is configured to support the rotation shaft in a non-contact state. The bearing member is fixed on the base member. The driving unit is configured to rotate the rotation shaft. The damping device includes a rail connected to the base member and a slider connected to the rotation shaft, and is configured to produce a damping force against a relative operation between the rotation shaft and the base member by a resistance generated between the rail and the slider.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
20230402415 · 2023-12-14 ·

Disclosed in the present disclosure are a semiconductor device and manufacturing method thereof. The method comprises: bonding the front surface of a top wafer to the front surface of a first wafer, and enabling the front surface of the top wafer to face upwards and the front surface of the first wafer to face downwards; bonding the front surface of a second wafer to the back surface of the first wafer to form a bonding structure, and enabling the front surface of the second wafer to face downwards; flipping the bonding structure to enable the front surface of the first wafer and the front surface of the second wafer to face upwards, and forming a pad pin in a top chip substrate.

Methods for processing a wide band gap semiconductor wafer, methods for forming a plurality of thin wide band gap semiconductor wafers, and wide band gap semiconductor wafers

A method for processing a wide band gap semiconductor wafer is proposed. The method includes depositing a non-monocrystalline support layer at a back side of a wide band gap semiconductor wafer, depositing an epitaxial layer at a front side of the wide band gap semiconductor wafer, and splitting the wide band gap semiconductor wafer along a splitting region to obtain a device wafer including at least a part of the epitaxial layer, and a remaining wafer including the non-monocrystalline support layer.

BONDED SUBSTRATE INCLUDING POLYCRYSTALLINE DIAMOND FILM
20210283881 · 2021-09-16 ·

A wafer has a layer containing silicon, a layer of polycrystalline diamond deposited on the silicon-containing layer, and a bow-compensation layer on the other side of the silicon-containing layer for reducing wafer-bow. A method of making a bonded structure includes an activation process for creating dangling bonds on the surface of one substrate, followed by contact-bonding the surface to a second substrate at low temperature. A bonded structure may include two substrates contact bonded to each other, one substrate including a layer containing silicon, a layer of polycrystalline diamond, a bow-compensation layer for reducing wafer-bow of the first substrate, and the other substrate including gallium nitride, silicon carbide, lithium niobate, lithium tantalate, gallium arsenide, indium phosphide, or another suitable material other than diamond.

Wafer production method

A method for producing a layer of solid material includes: providing a solid body having opposing first and second surfaces, the second surface being part of the layer of solid material; generating defects by means of multiphoton excitation caused by at least one laser beam penetrating into the solid body via the second surface and acting in an inner structure of the solid body to generate a detachment plane, the detachment plane including regions with different concentrations of defects; providing a polymer layer on the solid body; and subjecting the polymer layer to temperature conditions to generate mechanical stress in the solid body, including cooling of the polymer layer to a temperature below ambient temperature, the cooling taking place such that due to stresses a crack propagates in the solid body along the detachment plane and the layer of solid material separates from the solid body along the crack.

MASKING A ZONE AT THE EDGE OF A DONOR SUBSTRATE DURING AN ION IMPLANTATION STEP
20210143052 · 2021-05-13 ·

A process for forming a predetermined separation zone inside a donor substrate, in particular, to be used in a process of transferring a layer onto a carrier substrate comprises an implantation step that is carried out such that the implantation dose in a zone of the edge of the donor substrate is lower than the implantation dose in a central zone of the donor substrate to limit the formation of particles during thermal annealing. The present disclosure also relates to a donor substrate for a process of transferring a thin layer onto a carrier substrate produced by means of the process described above. The present disclosure also relates to a device for limiting an implantation region to a zone of the edge of a donor substrate.

Bonding method, bonding device, and holding member

A method for bonding a first substrate and a second substrate includes: forming a protrusion at a partial region of the first substrate; measuring a position of the first substrate after the protrusion is formed in the first substrate; and bonding the first substrate and the second substrate by contacting the protrusion of the first substrate with a surface of the second substrate to form a contact region and enlarging the contact region.

SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.