The present application provides a method for manufacturing an integrated metal resistance layer, comprising: step 1, selecting a formation position of a metal resistance layer, wherein the formation position of the metal resistance layer is located on the surface of an interlayer film inlaid with a copper connection; step 2, completing formation processes of the selected copper connection and the selected interlayer film; step 3, forming the metal resistance layer, comprising the following sub-steps: step 31, depositing a material layer of the metal resistance layer; and step 32, performing patterned etching on the material layer of the metal resistance layer to form the metal resistance layer in the selected region; and step 4, forming a next copper connection and a via at the bottom of the next copper connection, wherein the vias at the bottom of the next copper connection have two different heights.

A device may include: a highly doped n.sup.+ Si region; an intrinsic silicon multiplication region disposed on at least a portion of the n.sup.+ Si region, the intrinsic silicon multiplication having a thickness of about 90-110 nm; a highly doped p.sup.− Si charge region disposed on at least part of the intrinsic silicon multiplication region, the p.sup.− Si charge region having a thickness of about 40-60 nm; and a p.sup.+ Ge absorption region disposed on at least a portion of the p.sup.− Si charge region; wherein the p.sup.+ Ge absorption region is doped across its entire thickness. The thickness of the n.sup.+ Si region may be about 100 nm and the thickness of the p.sup.− Si charge region may be about 50 nm. The p.sup.+ Ge absorption region may confine the electric field to the multiplication region and the charge region to achieve a temperature stability of 4.2 mV/°C.

An epitaxial growth process for a semiconductor device includes providing a semiconductor substrate, forming a plurality of Dummy Gate structures on the surface of the semiconductor substrate, and forming grooves in a self-aligned manner on both sides of the Dummy Gate structures; forming an initial seed layer on the inner side surfaces of the grooves, the thickness of the formed initial seed layer on the bottoms of the grooves being greater and the thickness of the formed initial seed layer on the sidewalls being smaller since the growth speed of crystal faces <100> and <110> is different; longitudinally etching the initial seed layer to thin the bottom of the initial seed layer to form a seed layer; forming a main body layer on the seed layer, the main body layer filling the grooves; and forming a cover layer on the main body layer.

An epitaxial growth process for a semiconductor device includes providing a semiconductor substrate, forming a plurality of Dummy Gate structures on the surface of the semiconductor substrate, and forming grooves in a self-aligned manner on both sides of the Dummy Gate structures; forming an initial seed layer on the inner side surfaces of the grooves, the thickness of the formed initial seed layer on the bottoms of the grooves being greater and the thickness of the formed initial seed layer on the sidewalls being smaller since the growth speed of crystal faces <100> and <110> is different; longitudinally etching the initial seed layer to thin the bottom of the initial seed layer to form a seed layer; forming a main body layer on the seed layer, the main body layer filling the grooves; and forming a cover layer on the main body layer.

A device, a system and a method for bonding two substrates. A first substrate holder has a recess and an elevation.

A buffer layer on a silicon carbide substrate and a method of forming the same are disclosed. The buffer layer includes at least two layers of silicon carbide films, in which at least each lower one is doped at a top surface thereof with predetermined ions. As a result, at the top surface of the silicon carbide film, a barrier with different parameter is formed, which can block dislocation defects that have spread into the silicon carbide film from further upward propagation in the silicon carbide film.

A transistor using patterned metamaterial electrode manipulating electromagnetic waves to achieve matched phase velocity on the input and output ports. A design method is taught wherein the layout of the electrodes can be designed to compensate for the phase-velocity mismatch induced by the transistor's intrinsic properties.

A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

Disclosed herein are techniques for bonding LED components. According to certain embodiments, a first component including a semiconductor layer stack is hybrid bonded to a second component including a substrate that has a different thermal expansion coefficient than the semiconductor layer stack. The semiconductor layer stack includes an n-side semiconductor layer, an active light emitting layer, and a p-side semiconductor layer. The first component and the second component further include first contacts and second contacts, respectively. To hybrid bond the two components, the first contacts are aligned with the second contacts. Then dielectric bonding is performed to bond respective dielectric materials of both components. The dielectric bonding is followed by metal bonding of the contacts, using annealing. To compensate run-out between the first contacts and the second contacts, aspects of the present disclosure relate to changing a curvature of the first component and/or the second component during the annealing stage.