Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

A method for improving wafer bonding strength includes: Step S1: providing a silicon-based bonded wafer; Step S2: placing the bonded wafer in a microwave generating chamber; Step S3: raising the temperature in the microwave generating chamber and maintaining the temperature at a preset threshold by microwave heating; Step S4: after the bonded wafer reaches a predetermined temperature for a predetermined time period, shutting down the microwave power; and Step S5: cooling the bonded wafer. The present invention method can prevent waste of energy in the case of heating a small number of bonded wafers, and avoid a time-consuming preheating process. Therefore, the disclosed method is time-efficient and high-performance.

A method for improving wafer bonding strength includes: Step S1: providing a silicon-based bonded wafer; Step S2: placing the bonded wafer in a microwave generating chamber; Step S3: raising the temperature in the microwave generating chamber and maintaining the temperature at a preset threshold by microwave heating; Step S4: after the bonded wafer reaches a predetermined temperature for a predetermined time period, shutting down the microwave power; and Step S5: cooling the bonded wafer. The present invention method can prevent waste of energy in the case of heating a small number of bonded wafers, and avoid a time-consuming preheating process. Therefore, the disclosed method is time-efficient and high-performance.

A front surface element structure is formed on the front surface side of an n.sup.-type semiconductor substrate. Then defects are formed throughout an n.sup.-type semiconductor substrate to adjust a carrier lifetime. Hydrogen ions are ion-implanted from a rear surface side of the n.sup.-type semiconductor substrate, and a hydrogen implanted region having a hydrogen concentration higher than a hydrogen concentration of a bulk substrate is formed in the surface layer of a rear surface side of the n.sup.-type semiconductor substrate.

A PSG film, which is a silicon dioxide thin film containing phosphorus as a dopant, is formed on the surface of a semiconductor wafer. The semiconductor wafer having the PSG film formed thereon is kept at a predetermined heating temperature by light radiation from halogen lamps in the atmosphere containing hydrogen for 1 second or longer, so that the dopant is diffused from the PSG film into the surface of the semiconductor wafer. In addition, the flashing light is radiated to the semiconductor wafer for the radiation time shorter than 1 second to heat the surface of the semiconductor wafer to the target temperature so as to activate the dopant. When the PSG film is heated in the atmosphere containing hydrogen, a diffusion coefficient of the dopant contained in the PSG film becomes high; therefore, the dopant can be efficiently diffused from the PSG film into the semiconductor wafer.

A Lateral Diffusion Metal Oxide Semiconductor (LDMOS) device and its manufacturing method are presented. The LDMOS device comprises a first region that has a first conductivity type; a drift region that has a second conductivity type in the first region, wherein the second conductivity type is opposite to the first conductivity type; and a plurality of second regions that have the first conductivity type in the drift region, wherein the second regions are separated from each other and extend to the first region along a depth direction of the drift region. This LDMOS device has an higher Breakdown Voltage and thus better performance than conventional LDMOS devices.

Methods and systems for direct atomic layer etching and deposition on or in a substrate using charged particle beams. Electrostatically-deflected charged particle beam columns can be targeted in direct dependence on the design layout database to perform atomic layer etch and atomic layer deposition, expressing pattern with selected 3D-structure. Reducing the number of process steps in patterned atomic layer etch and deposition reduces manufacturing cycle time and increases yield by lowering the probability of defect introduction. Local gas and photon injectors and detectors are local to corresponding columns, and support superior, highly-configurable process execution and control.

Methods and systems for direct atomic layer etching and deposition on or in a substrate using charged particle beams. Electrostatically-deflected charged particle beam columns can be targeted in direct dependence on the design layout database to perform atomic layer etch and atomic layer deposition, expressing pattern with selected 3D-structure. Reducing the number of process steps in patterned atomic layer etch and deposition reduces manufacturing cycle time and increases yield by lowering the probability of defect introduction. Local gas and photon injectors and detectors are local to corresponding columns, and support superior, highly-configurable process execution and control.

Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.

Process kits, processing chambers, and methods for processing a substrate are provided. The process kit includes an edge ring, an adjustable tuning ring, and an actuating mechanism. The edge ring has a first ring component interfaced with a second ring component that is movable relative to the first ring component forming a gap therebetween. The second ring component has an inner thickness that is less than an outer thickness, and at least a portion of an upper surface of the second ring component is inwardly angled towards the ring first component. The adjustable tuning ring has an upper surface that contacts the lower surface of the second ring component. The actuating mechanism is interfaced with the lower surface of the adjustable tuning ring and is configured to actuate the adjustable tuning ring such that the gap between the first ring component and the second ring component is varied.