A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.

A method for removing crystal originated particles from a crystalline silicon body having opposite first and second surfaces includes: increasing a surface area of at least one of the first and second surfaces by an etch process; and oxidizing the increased surface area at a temperature of at least 1000 C. and for a duration of at least 20 minutes.

A transistor component includes in a semiconductor body a source zone and a drift zone of a first conduction type, and a body zone of a second conduction type complementary to the first conduction type, the body zone arranged between the drift zone and the source zone. The transistor component further includes a source electrode in contact with the source zone and the body zone, a gate electrode adjacent the body zone and dielectrically insulated from the body zone by a gate dielectric layer, and a diode structure connected between the drift zone and the source electrode. The diode structure includes a first emitter zone adjoining the drift zone in the semiconductor body, and a second emitter zone of the first conduction type adjoining the first emitter zone. The second emitter zone is connected to the source electrode and has an emitter efficiency of less than 0.7.

A laser beam irradiation unit of laser processing apparatus includes a pulse laser beam oscillating unit, a condenser that condenses a pulse laser beam and emits the beam to a workpiece held by a chuck table, a dichroic mirror disposed between the pulse laser beam oscillating unit and the condenser, a strobe light irradiation unit that emits light to a path on which the dichroic mirror and the condenser are disposed, a beam splitter disposed between the strobe light irradiation unit and the dichroic mirror, and an imaging unit disposed on the path of light split by the beam splitter. A controller actuates the strobe light irradiation unit and the imaging unit according to the timing of the pulse laser beam, and detects the width of a laser-processed groove immediately after emission of the pulse laser beam on the basis of an image signal from the imaging unit.

Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

A semiconductor device may include an element region and a peripheral voltage withstanding region. The peripheral voltage withstanding region includes inner circumferential guard rings; and outer circumferential guard rings having a width narrower than a width of the inner circumferential guard rings. An interval between the inner circumferential guard rings is narrower than an interval between the outer circumferential guard rings. Each of the inner circumferential guard rings includes a first high concentration region and a first low concentration region. Each of the outer circumferential guard rings includes a second high concentration region and a second low concentration region. A width of a part of each first low concentration region that is exposed on a front surface of the semiconductor device is wider than a width of a part of each second low concentration region that is exposed on the front surface.

Provided is a Precision Voltage Reference (PVR). In one example, the PVR includes a resonator having an oscillation frequency, the resonator including a first proof-mass, a first forcer located adjacent a first side of the first proof-mass, and a second forcer located adjacent a second side of the first proof-mass. The PVR may include control circuitry configured to generate a reference voltage based on the oscillation frequency of the resonator, at least one converter configured to receive the reference voltage from the control circuitry, provide a first bias voltage to the first forcer based on the reference voltage, provide a second bias voltage to the second forcer based on the reference voltage, and periodically alter a polarity of the first and second bias voltages to drive the oscillation frequency to match a reference frequency, and an output configured to provide the reference voltage as a voltage reference signal.

An assembly present in an ion source for supporting an arc chamber upon a base plate includes a first arc support plate, a first screw, and a second screw. The first screw passes through a smooth through-hole in an arm of the first arc support plate and extends into a bore in the base plate. The second (or adjustable) screw passes through a threaded through-hole in an arm of the first arc support plate and engages an upper surface of the base plate itself, and can be used to change the altitude and angle of the first arc support plate relative to the base plate. This adjustment ability improves the beam quality of the ion source.

An assembly present in an ion source for supporting an arc chamber upon a base plate includes a first arc support plate, a first screw, and a second screw. The first screw passes through a smooth through-hole in an arm of the first arc support plate and extends into a bore in the base plate. The second (or adjustable) screw passes through a threaded through-hole in an arm of the first arc support plate and engages an upper surface of the base plate itself, and can be used to change the altitude and angle of the first arc support plate relative to the base plate. This adjustment ability improves the beam quality of the ion source.