In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.

A memory device with a dielectric blocking layer for improving interpoly dielectric breakdown is provided. Embodiments include.

A memory device with a dielectric blocking layer for improving interpoly dielectric breakdown is provided. Embodiments include.

A prober includes: a stage that places a substrate formed with a plurality of chips thereon in a matrix; a contact that sequentially contacts with electrode pads of the plurality of chips thereby performing an inspection on electrical characteristic of the plurality of chips; a plurality of LED units provided on a side opposite to a placing surface of the stage so as to independently heat a plurality of areas where the plurality of chips are located, respectively, and each including one or a plurality of LEDs; and a controller that outputs a control signal to drive, among the plurality of LED units, at least an LED unit corresponding to an area of a chip to be inspected, among the area of the chip to be inspected and peripheral areas of the corresponding area.

Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.

A method for reducing defects of an electronic component using a supercritical fluid includes recrystallizing and rearranging grains in the electronic component by introducing the supercritical fluid doped with H.sub.2S together with an electromagnetic wave into a cavity. The cavity has a temperature above a critical temperature of the supercritical fluid and a pressure above a critical pressure of the supercritical fluid.

A method for reducing defects of an electronic component using a supercritical fluid includes recrystallizing and rearranging grains in the electronic component by introducing the supercritical fluid doped with H.sub.2S together with an electromagnetic wave into a cavity. The cavity has a temperature above a critical temperature of the supercritical fluid and a pressure above a critical pressure of the supercritical fluid.

An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.