The present invention generally describes apparatuses and methods used to perform an annealing process on desired regions of a substrate. In one embodiment, pulses of electromagnetic energy are delivered to a substrate using a flash lamp or laser apparatus. The pulses may be from about 1 nsec to about 10 msec long, and each pulse has less energy than that required to melt the substrate material. The interval between pulses is generally long enough to allow the energy imparted by each pulse to dissipate completely. Thus, each pulse completes a micro-anneal cycle. The pulses may be delivered to the entire substrate at once, or to portions of the substrate at a time. Further embodiments provide an apparatus for powering a radiation assembly, and apparatuses for detecting the effect of pulses on a substrate.

An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length l and the channel width w, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.

An integrated circuit includes a plurality of low-voltage FinFET transistors each having a channel length l and a channel width w, the low-voltage FinFET transistors having a first threshold voltage channel implant and a first gate dielectric thickness. The integrated circuit also includes a plurality of high-voltage FinFET transistors each having the channel length l and the channel width w, the high-voltage FinFET transistors having a second threshold voltage channel implant greater than the first threshold voltage channel implant and second gate dielectric thickness greater than the first gate dielectric thickness.

A method of patterning a substrate may include providing a cavity in a layer, disposed on the substrate. The cavity may have a first length along a first direction and a first width along a second direction, perpendicular to the first direction. The method may include directing first angled ions in a first exposure to the cavity, wherein after the first exposure the cavity has a second length, greater than the first length; directing normal ions in a second exposure to the cavity, wherein the cavity retains the second length after the second exposure; and directing second angled ions to the cavity is a third exposure, subsequent to the second exposure, wherein the cavity has a third length, greater than the second length, after the third exposure.

A transient-voltage-suppression diode structure and a manufacturing method thereof are disclosed. The structure includes a substrate, an N− type epitaxial layer, a first metal layer, a first N+ type implant layer, a deep N+ type implant layer and plural polycrystalline plugs. The N− type epitaxial layer is disposed on the substrate. The first metal layer is disposed on the N− type epitaxial layer to form a working-voltage terminal. The first N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N− type epitaxial layer is connected with the working-voltage terminal. The deep N+ type implant layer spatially corresponding to the working-voltage terminal and embedded in the N− type epitaxial layer is spaced apart from the first N+ type implant layer at a separation distance. The plural polycrystalline plugs are connected between the working-voltage terminal of the first metal layer and the deep N+ type implant layer.

A substrate processing a technology including: a substrate holder; a tubular reactor that houses the substrate holder; an inlet flange connected to the tubular reactor including a plurality of gas introduction ports; a lid that closes a lower opening of the inlet flange in a manner such that the substrate holder can be carried in and out; heater elements disposed along the outer peripheral surface of the inlet flange while avoiding the gas introduction ports; temperature sensors thermally coupled to the inlet flange or any heater element and adapted to detect temperatures; and a temperature controller that divides of the heater elements into groups and controls power supply to the respective heater elements independently for each of the groups based on temperatures detection temperatures detected by the temperature sensors.

The various technologies presented herein relate to measuring a signal generated by a die-based test circuit incorporated into an IC and utilizing the measured signal to authenticate the IC. The signal can be based upon a sensor response generated by the test circuit fabricated into the die, wherein the sensor response is based upon a property of the die material. The signal can be compared with a reference value obtained from one or more test circuit(s) respectively located on one or more reference dies, wherein the reference dies are respectively cut from different wafers, and the location at which the reference dies were cut is known. If the measured signal matches the reference value, the die is deemed to be from the same cut location as the dies from which the reference value was obtained. If the measured signal does not match the reference value, the die is not authenticated.

A prober includes: a stage that places a substrate formed with a plurality of chips thereon in a matrix; a contact that sequentially contacts with electrode pads of the plurality of chips thereby performing an inspection on electrical characteristic of the plurality of chips; a plurality of LED units provided on a side opposite to a placing surface of the stage so as to independently heat a plurality of areas where the plurality of chips are located, respectively, and each including one or a plurality of LEDs; and a controller that outputs a control signal to drive, among the plurality of LED units, at least an LED unit corresponding to an area of a chip to be inspected, among the area of the chip to be inspected and peripheral areas of the corresponding area.

A method for evaluating a carbon concentration where ions of a predetermined element are implanted into a silicon wafer, and then a carbon concentration is measured by a low-temperature PL method from an emission intensity of a CiCs composite, where the ions are implanted under implantation conditions of 1.110.sup.11[atomic weight of the implanted element].sup.0.73<implantation amount (cm.sup.2)<4.310.sup.11[atomic weight of the implanted element].sup.0.73, and the carbon concentration is evaluated. A method for evaluating a carbon concentration makes it possible to measure with high sensitivity, a carbon concentration in a surface layer of 1 to 2 m which is a photodiode region in an image sensor.

Method for preparing site-specific, plan-view lamellae from multilayered microelectronic devices. A focused ion beam that is directed, with an etch-assisting gas, toward an uppermost layer of a device removes at least that uppermost layer and thereby exposes an underlying layer over, or comprising, a target area from which the site-specific, plan-view lamella is to be prepared, wherein the focused ion beam is in a face-on orientation in removing the uppermost layer to expose the underlying layer. In a preferred embodiment, the etch-assisting gas comprises methyl nitroacetate. In alternative embodiments, the etch-assisting gas is methyl acetate, ethyl acetate, ethyl nitroacetate, propyl acetate, propyl nitroacetate, nitro ethyl acetate, methyl methoxyacetate, or methoxy acetylchloride.