H01L21/26

Defect detection structure of a semiconductor die, semiconductor device including the same and method of detecting defects in semiconductor die

A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Semiconductor structure and method of manufacturing the same

A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantation cycles in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.

TESTING DEVICE
20200408828 · 2020-12-31 ·

A testing device for inspecting an electronic device by causing contact terminals to electrically contact the electronic device, includes: a mounting table formed with a light transmission member opposite the side on which a inspection object is placed and having therein a coolant flow path through which a coolant capable of transmitting light flows; a light irradiation mechanism disposed so as to face the surface opposite the inspection object placement side of the mounting table, and having LEDs pointing toward the inspection object; and a controller controlling absorption of heat by the coolant and heating by the lights from the LEDs to control the temperature of the electronic device to be inspected. The controller controls the light output from the LEDs based on the measured temperature of the electronic device to be inspected and controls the absorption of heat by the coolant based on the LED light output.

TESTING DEVICE
20200408828 · 2020-12-31 ·

A testing device for inspecting an electronic device by causing contact terminals to electrically contact the electronic device, includes: a mounting table formed with a light transmission member opposite the side on which a inspection object is placed and having therein a coolant flow path through which a coolant capable of transmitting light flows; a light irradiation mechanism disposed so as to face the surface opposite the inspection object placement side of the mounting table, and having LEDs pointing toward the inspection object; and a controller controlling absorption of heat by the coolant and heating by the lights from the LEDs to control the temperature of the electronic device to be inspected. The controller controls the light output from the LEDs based on the measured temperature of the electronic device to be inspected and controls the absorption of heat by the coolant based on the LED light output.

Methods for fabricating transistor and ESD device

Methods for fabricating a transistor and an electro-static discharge (ESD) device are provided. In a method, a first well area doped with a first well ion is formed in a base substrate. A second well area is doped with a second well ion in the base substrate. The second well area includes a first region adjacent to the first well area. A first ion doping region doped with first ions is formed in the first well area and the first region. A type of the first ions is the same as a type of the first well ion and opposite to a type of the second well ion. A gate structure is formed on a part of the first well area and at least a part of the first region.

Methods and apparatus for fabricating IC chips with tilted patterning
10854455 · 2020-12-01 · ·

The present disclosure describes methods and apparatuses for fabricating integrated-circuit (IC) die with tilted patterning. In some aspects, mandrels are fabricated on a material stack and occlude portions of a layer of material from a field of energy radiated at an angle of incidence relative to the mandrels. The occluded portions of the layer of material can be used to mask an underlying film to create a film pattern on a substrate of the IC die. These methods and apparatuses may enable the fabrication of IC die with features that are smaller in size than those afforded by conventional lithography processes.

Method of manufacturing a semiconductor device in which a lifetime of carriers is controlled

A front surface element structure is formed on the front surface side of an n.sup.-type semiconductor substrate. Then defects are formed throughout an n.sup.-type semiconductor substrate to adjust a carrier lifetime. Hydrogen ions are ion-implanted from a rear surface side of the n.sup.-type semiconductor substrate, and a hydrogen implanted region having a hydrogen concentration higher than a hydrogen concentration of a bulk substrate is formed in the surface layer of a rear surface side of the n.sup.-type semiconductor substrate.

METHODS AND APPARATUS FOR MINIMIZING SUBSTRATE BACKSIDE DAMAGE

Embodiments of the present disclosure generally relate to apparatus and methods for reducing substrate backside damage during semiconductor device processing. In one implementation, a method of chucking a substrate in a substrate process chamber includes exposing the substrate to a plasma preheat treatment prior to applying a chucking voltage to a substrate support. In one implementation, a substrate support is provided and includes a body having an electrode and thermal control device disposed therein. A plurality of substrate supporting features are formed on an upper surface of the body, each of the substrate supporting features having a substrate supporting surface and a rounded edge.

METHODS AND APPARATUS FOR MINIMIZING SUBSTRATE BACKSIDE DAMAGE

Embodiments of the present disclosure generally relate to apparatus and methods for reducing substrate backside damage during semiconductor device processing. In one implementation, a method of chucking a substrate in a substrate process chamber includes exposing the substrate to a plasma preheat treatment prior to applying a chucking voltage to a substrate support. In one implementation, a substrate support is provided and includes a body having an electrode and thermal control device disposed therein. A plurality of substrate supporting features are formed on an upper surface of the body, each of the substrate supporting features having a substrate supporting surface and a rounded edge.

Wafer processing tool having a micro sensor
10818564 · 2020-10-27 · ·

Embodiments include devices and methods for detecting material deposition and material removal performed by a wafer processing tool. In an embodiment, one or more micro sensors mounted on a process chamber of the wafer processing tool are capable of operating under vacuum conditions and/or may measure material deposition and removal rates in real-time during a plasma-less wafer fabrication process. Other embodiments are also described and claimed.