Methods to improve front-side process uniformity by back-side metallization are disclosed. In some implementations, a metal layer is deposited on the back-side of a wafer prior to performing a plasma-based process on the front side of the wafer. Presence of the back-side metal layer reduces variations in, for example, thickness of a deposited and/or etched layer resulting from the plasma-based process.

Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in source/drain regions on fin portions. The fin portions can be located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions can be oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

Oxide-free, low temperature wafer bonding permits electric current to cross the covalently bonded interface unimpeded by traps, recombination centers and unintentional, defect-induced blocking barriers when interfacial defects are passivated by hydrogen diffused from shallow implants towards the interface. Systems and methods comprising oxide-free, low temperature covalent wafer bonding with passivated interface states are used in various applications requiring reduced interfacial scattering and carrier trapping and efficient charge collection across bonded interfaces.

To detach a substrate from a table without damaging the substrate. According to Embodiment 1, provided is a substrate processing apparatus including a table to hold a substrate, a plurality of lift pins that are arranged at periphery of the table and configured to arrange or separate the substrate on or from the table and to be movable in a direction perpendicular to a surface of the table, a drive mechanism that includes a motor to move the lift pins in the direction perpendicular to the surface of the table, and a control device that is configured to control the drive mechanism. The control device is configured to be capable of moving the lift pins at a first speed and at a second speed different from the first speed.

To detach a substrate from a table without damaging the substrate. According to Embodiment 1, provided is a substrate processing apparatus including a table to hold a substrate, a plurality of lift pins that are arranged at periphery of the table and configured to arrange or separate the substrate on or from the table and to be movable in a direction perpendicular to a surface of the table, a drive mechanism that includes a motor to move the lift pins in the direction perpendicular to the surface of the table, and a control device that is configured to control the drive mechanism. The control device is configured to be capable of moving the lift pins at a first speed and at a second speed different from the first speed.

Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n.sup.+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.

In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.

Methods for forming an interconnections structure on a substrate in a cluster processing system and thermal processing such interconnections structure are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a barrier layer in an opening formed in a material layer disposed on a substrate, forming an interface layer on the barrier layer, forming a gap filling layer on the interface layer, and performing an annealing process on the substrate, wherein the annealing process is performed at a pressure range greater than 5 bar.

A miller, a non-transitory computer-readable medium, and a method for milling a multi-layered object. The method may include milling each structural element of an array of structural elements that are spaced apart from each other by gaps to provide the milled structural elements, wherein each milled structural element has a flat upper surface, wherein prior the milling each one of the structural elements of the array has a flat upper surface of a certain width, wherein the certain width is of a nanometric scale. The milling of each structural element of the array may include scanning a defocused ion beam of the certain width along a longitudinal axis of the structural element. A current intensity of the defocused ion beam decreases with a distance from a middle of the defocused ion beam.

A miller, a non-transitory computer-readable medium, and a method for milling a multi-layered object. The method may include milling each structural element of an array of structural elements that are spaced apart from each other by gaps to provide the milled structural elements, wherein each milled structural element has a flat upper surface, wherein prior the milling each one of the structural elements of the array has a flat upper surface of a certain width, wherein the certain width is of a nanometric scale. The milling of each structural element of the array may include scanning a defocused ion beam of the certain width along a longitudinal axis of the structural element. A current intensity of the defocused ion beam decreases with a distance from a middle of the defocused ion beam.