To detach a substrate from a table without damaging the substrate. According to Embodiment 1, provided is a substrate processing apparatus including a table to hold a substrate, a plurality of lift pins that are arranged at periphery of the table and configured to arrange or separate the substrate on or from the table and to be movable in a direction perpendicular to a surface of the table, a drive mechanism that includes a motor to move the lift pins in the direction perpendicular to the surface of the table, and a control device that is configured to control the drive mechanism. The control device is configured to be capable of moving the lift pins at a first speed and at a second speed different from the first speed.

To detach a substrate from a table without damaging the substrate. According to Embodiment 1, provided is a substrate processing apparatus including a table to hold a substrate, a plurality of lift pins that are arranged at periphery of the table and configured to arrange or separate the substrate on or from the table and to be movable in a direction perpendicular to a surface of the table, a drive mechanism that includes a motor to move the lift pins in the direction perpendicular to the surface of the table, and a control device that is configured to control the drive mechanism. The control device is configured to be capable of moving the lift pins at a first speed and at a second speed different from the first speed.

Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a non-planar channel region is formed having a first semiconductor layer, a second semiconductor layer, and a fin-shaped bridge layer between the first semiconductor layer and the second semiconductor layer. Forming the non-planar channel region can include forming a nanosheet stack over a substrate, forming a trench by removing a portion of the nanosheet stack, and forming a third semiconductor layer in the trench. Outer surfaces of the first semiconductor layer, the second semiconductor layer, and the fin-shaped bridge region define an effective channel width of the non-planar channel region.

A display device manufacturing method and a display device manufacturing apparatus are provided. The method includes steps A to D. The step A includes forming a display device. The step B includes disposing the display device in a sealing chamber. The step C includes adding hydrogen gas into the sealing chamber such that hydrogen atoms in the hydrogen gas spread in an insulating layer. The step D includes heating the hydrogen gas and/or the display device in sealing chamber such that the hydrogen atoms in insulating layer spread in the semiconductor member. The present invention can enhance electrical performance of the semiconductor member.

A method according to some embodiments of the present disclosure includes providing a workpiece that include an opening and a top surface, depositing a dielectric material over the workpiece and into the opening to form a first dielectric layer that has a top portion over the top surface and a plug portion in the opening, treating the first dielectric layer to convert top portion into a second dielectric layer different from the first dielectric layer, and selectively removing the second dielectric layer.

Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45 angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.

A manufacturing method of an epitaxial silicon wafer uses a silicon wafer containing phosphorus, having a resistivity of less than 1.0 m.Math.cm. The silicon wafer has a main surface to which a (100) plane is inclined and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 05 to 025 with respect to an axis orthogonal to the main surface. The manufacturing method includes: annealing the silicon wafer at a temperature from 1200 degrees C. to 1220 degrees C. for 30 minutes or more under argon gas atmosphere (argon-annealing step); etching a surface of the silicon wafer (prebaking step); and growing the epitaxial film at a growth temperature ranging from 1100 degrees C. to 1165 degrees C. on the surface of the silicon wafer (epitaxial film growth step).

The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

There is provided a semiconductor device comprising: a semiconductor substrate; an emitter region of a first conductivity type provided inside the semiconductor substrate; a base region of a second conductivity type provided below the emitter region inside the semiconductor substrate; an accumulation region of the first conductivity type provided below the base region inside the semiconductor substrate, and containing hydrogen as an impurity; and a trench portion provided to pass through the emitter region, the base region and the accumulation region from an upper surface of the semiconductor substrate.