An image sensor array formed on a flexible first substrate is supported by a flexible second substrate attached thereto. The second substrate has a top surface with an adhesive thereon for attaching the substrates together. The adhesive is on a portion of the second substrate directly beneath the image sensor array to allow selective formation of the second substrate.

A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating. After the removing, the pattern-interrupting second feature in the lower substrate material is used as a reference location to reckon which of the two different composition masking materials was used to make first spaces between the first features in an analysis area in the material that was above the lower substrate material or which of the two different composition masking materials was used to make second spaces between the first features in the analysis area that alternate with the first spaces. Structure independent of method is disclosed.

A process for handling MEMS wafers includes the steps of: (i) attaching a first carrier substrate to a first side of a MEMS wafer, the first carrier substrate being attached via a first wafer bonding tape and a silicone-free peel tape, the peel tape contacting the first side of the MEMS wafer; (ii) performing wafer processing steps on an opposite second side of the MEMS wafer; (iii) releasing the first carrier substrate from the first side of the MEMS wafer via exposure to an energy source, the energy source selectively releasing the wafer bonding tape from the first side of the MEMS wafer; and (iv) peeling the peel tape away from the first side of the MEMS wafer.

A processing apparatus for an electronic component includes a component holder configured to hold the electronic component, a turning unit configured to hold the component holder toward an outside of a predetermined circular track, a turning drive unit configured to turn the turning unit around a first axis along a central axis of the circular track, and a rotation drive unit provided on the turning unit and configured to rotate the component holder around a second axis along a radial direction of the circular track.

Methods of semiconductor processing may include performing a process on a semiconductor substrate. The semiconductor substrate may be seated on a substrate support positioned within a processing region of a semiconductor processing chamber. The methods may include flowing a first backside gas through the substrate support at a first flow rate. The methods may include removing the semiconductor substrate from the processing region of the semiconductor processing chamber. The methods may include performing a plasma cleaning operation within the processing region of the semiconductor processing chamber. The methods may include flowing a second backside gas through the substrate support at a second flow rate. At least a portion of the second backside gas may flow into the processing region through accesses in the substrate support.

Methods of semiconductor processing may include performing a process on a semiconductor substrate. The semiconductor substrate may be seated on a substrate support positioned within a processing region of a semiconductor processing chamber. The methods may include flowing a first backside gas through the substrate support at a first flow rate. The methods may include removing the semiconductor substrate from the processing region of the semiconductor processing chamber. The methods may include performing a plasma cleaning operation within the processing region of the semiconductor processing chamber. The methods may include flowing a second backside gas through the substrate support at a second flow rate. At least a portion of the second backside gas may flow into the processing region through accesses in the substrate support.

A branching element configured to branch a second laser light into a plurality of beams of branch light along a machining feed direction, and a second condenser lens configured to focus the plurality of beams of branch light branched by a branching element onto a street to be machined are provided, and a time period τ is expressed as τ=L/V, where L is a branch distance, which corresponds to spacing between adjacent leading and trailing spots for each of branch lights focused on the street by the second condenser lens, V is a machining speed, which corresponds to a speed of relative movement, and τ is the time period taken until the trailing spot overlaps a machining position of the leading spot, and τ>τ1 is satisfied, where τ1 is a threshold value of the time period when deterioration of the machining quality of the second groove occurs.

Methods, apparatuses, and systems for substrate processing for lowering contact resistance in at least contact pads of a semiconductor device are provided herein. In some embodiments, a method of substrate processing for lowering contact resistance of contact pads includes: circulating a cooling fluid in at least one channel of a pedestal; and exposing a backside of the substrate located on the pedestal to a cooling gas to cool a substrate located on the pedestal to a temperature of less than 70 degrees Celsius. In some embodiments in accordance with the present principles, the method can further include distributing a hydrogen gas or hydrogen gas combination over the substrate.

Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.

Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.