An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions.

Systems and methods for selectively etching features in an electronic substrate via a precision dispense apparatus and precision etchant dispense tool are disclosed. The method includes creating a toolpath instruction for etching at least one feature in the substrate, programming the precision dispense apparatus to execute the created toolpath instruction, and causing the precision dispense tool to deposit etchant material onto the surface of the substrate to etch the substrate surface to produce the at least one feature according to the created toolpath instruction. The capabilities of the systems and methods disclosed herein extend to 3D substrates and post-build processing, among others.

A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.

Semiconductor device packages and methods of manufacture are described. In one example, a semiconductor device package includes a flange, a frame secured to a major surface of the flange, with the frame forming an air cavity bounded in part by a surface of the flange, and at least one conductive lead that extends from outside the frame, through a portion of the frame, and is exposed within the air cavity for wire bonding. Other packages without air cavities are also described. The flange can incorporate a composite core material including diamond particles distributed in metal. The flange offers improved thermal conductivity, for greater heat dissipation from and additional performance of semiconductor devices within the packages. The flange exhibits thermal conductivity greater than that of Copper and other materials. The flange also exhibits a coefficient of thermal expansion suitable for bonding semiconductor die including GaN and SiC materials to the flange.

A composition for forming a resist underlayer film includes: a solvent; and a polymer containing a unit structure (A) represented by formula (1). The composition is reduced in the amount of sublimated substances that contaminate a device, is improved in the in-plane uniform coatability of a film to be coated thereon, exhibits satisfactory resistance to a chemical solution used in a resist under layer film, and can exhibit other satisfactory properties.

Each of a plurality of terminals has a first portion and a second portion being a connection target for a semiconductor element. A manufacturing method of a housing includes a first step arranging, for a lower mold provided with a plurality of holes each of which is a target into which the first portion is inserted, a nest having a third portion covering at least one of the holes, a second step arranging, for the lower mold with the nest being arranged therein, the plurality of terminals by inserting the first portion into the hole not covered by the third portion, a third step arranging an upper mold on the lower mold with the nest and the plurality of terminals being arranged therein, and a fourth step, which is executed after the third step, obtaining the housing by performing resin molding using the lower mold and the upper mold.

A package structure includes an optical die, an optical die, a supporting structure, and a lens structure. The optical die includes a photonic region. The optical die is disposed on and electrically coupled to the optical die. The supporting structure is disposed on the optical die, where the electric die is disposed between the supporting structure and the optical die. The lens structure is disposed on the supporting structure and optically coupled to the photonic region of the optical die, where the supporting structure is disposed between the lens structure and the electric die.

An electrical connector is essentially composed of a pair of half housings opposite to each other in a longitudinal direction to commonly form a receiving cavity for receiving a CPU. Each half housing is equipped with a plurality of contacts with corresponding contacting sections upwardly extending into the receiving cavity for mating with the CPU. A single pick-up cap includes a plate with a plurality of claws adapted to be engaged within locking recesses in exterior sides of the half housings, a plurality of positioning blocks adapted to extend into the receiving cavity so as to cooperate with the claws to sandwich the periphery wall of the housing therebetween in the longitudinal direction for securing the half housings to the pick-up cap. Therefore, both the pair of half housings may be grasped by the single pick-up cap for mounting and soldering to PCB at the same time.

A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.