A method for forming a cavity in a silicon substrate, a surface of the silicon substrate having a tilting angle relative to a first plane of the silicon substrate, and the first plane being a {111} plane of the silicon substrate, and situation of an etching mask on the surface of the silicon substrate. The etching mask has a retarding structure that protrudes into the mask opening, and a first etching projection region. All further edges of the mask opening outside the first etching projection region are situated essentially parallel to {111} planes of the silicon substrate. The method includes an anisotropic etching of the silicon substrate during a defined etching duration. An etching rate in the <111> directions of the silicon substrate is lower than in other spatial directions, and the first retarding structure is undercut in a first undercut direction going out from the first etching projection region.

Some embodiments relate to a package. The package includes a first substrate, a second substrate, and an interposer frame between the first and second substrates. The first substrate has a first connection pad disposed on a first face thereof, and the second substrate has a second connection pad disposed on a second face thereof. The interposer frame is arranged between the first and second faces and generally separates the first substrate from the second substrate. The interposer frame includes a plurality of through substrate holes (TSHs) which pass entirely through the interposer frame. A TSH is aligned with the first and second connection pads, and solder extends through the TSH to electrically connect the first connection pad to the second connection pad.

A method of forming a bonding element including a first transient liquid phase (TLP) bonding element including a first material and a second material, the first material having a higher melting point than the second material, a ratio of a quantity of the first material and the second material in the first TLP bonding element having a first value, and a second TLP bonding element including the first material and the second material, a ratio of a quantity of the first material and the second material in the second TLP bonding element having a second value different from the first value.

A flat plate frame is formed, which is flat plate-shaped, which has an opening penetrating its front and rear surfaces and groove terminal patterns formed on its front surface, and which contains a semi-cured thermosetting resin. Then, an insulating substrate is disposed on the rear surface so as to cover the opening of the flat plate frame, external connection terminals are disposed on the terminal patterns, and heating is carried out. As a result, a terminal package to which the insulating substrate and external connection terminals are firmly joined is produced using the flat plate frame. The external connection terminals included in the terminal package are reliably and firmly joined to the terminal package. Therefore, the external connection terminals are not displaced when wires are bonded to the external connection terminals.

A flat plate frame is formed, which is flat plate-shaped, which has an opening penetrating its front and rear surfaces and groove terminal patterns formed on its front surface, and which contains a semi-cured thermosetting resin. Then, an insulating substrate is disposed on the rear surface so as to cover the opening of the flat plate frame, external connection terminals are disposed on the terminal patterns, and heating is carried out. As a result, a terminal package to which the insulating substrate and external connection terminals are firmly joined is produced using the flat plate frame. The external connection terminals included in the terminal package are reliably and firmly joined to the terminal package. Therefore, the external connection terminals are not displaced when wires are bonded to the external connection terminals.

In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

Provided is a method for manufacturing a metal-layer-joined ceramic base material board, in which at least one scribe line is formed, on each of the front and back surfaces of a ceramic base material board, along dividing lines for dividing the ceramic base material board into a plurality of ceramic boards, a metal board covering at least a portion of the dividing lines is joined to each of the front and back surface of the ceramic base material board, the metal boards are etched along the dividing lines to form a plurality of metal layers, and the plurality of metal layers are joined to each of the front and back surfaces of the ceramic base material board.

A semiconductor package structure includes a substrate, a semiconductor sensor, a lid and an air-permeable film. The semiconductor sensor is disposed on the substrate. The lid covers the semiconductor sensor and defines a through hole. The air-permeable film covers the through hole of the lid and has a first surface. The first surface is hydrophilic.

A method of making a semiconductor device assembly is provided. The method comprises attaching a first semiconductor device to an upper surface of a substrate and disposing a stencil over the upper surface of the substrate. The stencil includes (i) an opening and (ii) a cavity in which the first semiconductor device is disposed. The method further comprises screen-printing an epoxy material into the opening and onto the upper surface of the substrate, removing the stencil, and planarizing an upper surface of the epoxy material to form an epoxy spacer.

A heat dissipation substrate includes an insulating layer, a metal heat dissipation block, and a patterned structure layer. The insulating layer has a first surface, a second surface and at least one through hole. The metal heat dissipation block passes through the insulating layer from the second surface of the insulating layer and has an upper surface, a lower surface, and a contact surface. There is a first vertical height between the contact surface and the lower surface. The patterned structure layer includes a patterned circuit layer and at least one conductive structure layer. The patterned circuit layer is disposed on the first surface of the insulating layer, and the conductive structure layer is connected to the patterned circuit layer and extends to cover an inner wall of the through hole. The patterned circuit layer has a top surface, the conductive structure layer has a bottom surface. There is a second vertical height between the top surface and the first surface, and the first vertical height is 3 times to 300 times the second vertical height.