A chip card substrate is provided, which includes a plurality of layers. The plurality of layers includes a first polymer layer including a first polymer material, a second polymer layer disposed over the first polymer layer and a second polymer material different from the first polymer material. The plurality of layers further includes a third polymer layer disposed over the second polymer layer and including the first polymer material. The second polymer layer includes a plurality of cutouts at an edge of the second polymer layer so that the first polymer material of the first polymer layer and of the third polymer layer form a coupling through the plurality of cutouts.

A housing for a power semiconductor module arrangement includes sidewalls and a lid. The lid includes a first layer of a first material having a plurality of openings, and second layer of a second material that is different from the first material. The second layer completely covers a bottom surface of the first layer. The second layer includes a plurality of protrusions, each protrusion extending into a different one of the plurality of openings of the first layer such that each of the plurality of openings is completely covered by one of the protrusions.

A frame lid for use with a semiconductor package is disclosed. First, a mask is applied to a top surface of the lid and over a central area of the top surface to define a peripheral area. Next, a seal ring is formed by metallizing the peripheral area and the sidewall of the plate. The mask can then be removed obtain the frame lid. Next, a solder preform can be attached to the seal ring. This reduces pullback and shrinkage of the metallized layer, while lowering the manufacturing cost and process times.

A substrate structure, a package structure, and a method for manufacturing an electronic package structure provided. The substrate structure includes a dielectric layer, a trace layer, and at least one wettable flank. The dielectric layer has a first surface and a second surface opposite to the first surface. The trace layer is embedded in the dielectric layer and exposed from the first surface of the dielectric layer. The at least one wettable flank is stacked with a portion of the trace layer embedded in the dielectric layer.

A laminate substrate for receiving a semiconductor chip. Included are laminate layers stacked to form the laminate substrate, each laminate layer includes a core that includes particle-filled epoxy and a metallic layer on the core. At least one laminate layer has a radial cut through the metallic layer, the radial cut extending from a periphery of the at least one laminate layer towards a center of the at least one laminate layer. The radial cut cuts only through the metallic layer and does not cut through the core.

An electronic circuit component includes: an electronic component; a leadframe that forms a circuit pattern corresponding to an arrangement of the electronic component; a resin element in which a part of the leadframe is disposed by insert molding; a first lid element that covers a first surface of the resin element on which the electronic component is arranged, the first surface of the resin element including a concave land in which the electronic component is arranged; and terminal portions that are arranged on a bottom surface of the land. The terminal portions are a part of the leadframe and are electrically connected to the electronic component. A part of the first lid element that is opposed to the land includes a recess that defines a clearance between the electronic component and the first lid element.

A method for forming a metallization structure is provided, including forming a metallic powder layer on a substrate; performing a first laser sintering on a first portion of the metallic powder layer to form a metal layer; and in the presence of oxygen, performing a second laser sintering on a second portion of the metallic powder layer to form a metal oxide layer to serve as a first dielectric layer.

A method may include forming a cavity within a plastic structure with a channel positioned at a perimeter of the cavity, inserting the electronic component into the cavity, dispensing a dielectric fluid into the channel at the perimeter of the cavity, curing the dielectric fluid in situ to secure the electronic component within the cavity with a cured dielectric and printing interconnects for the electronic component.

Methods of forming a semiconductor device comprising a lead-frame having a die pad having at least one electrically conductive die pad area and an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

The present disclosure describes semiconductor packages and, more particularly, chip-embedded semiconductor packages. The packages include core panels with apertures extending through the core panel. Semiconductor chips are embedded within chip apertures. A molding compound can be positioned along one side of the core panel. In some examples, the semiconductor chips are embedded within the molding compound. In other examples, the semiconductor chips are adhered to the molding compound. The coefficient of thermal expansion (CTE) values of the core panels described herein can be tailored to decrease warpage of the package as the semiconductor chip heats during use.