A structure includes a semiconductor substrate having a through-substrate via (TSV) extending from a backside of the semiconductor substrate up to an insulator layer disposed on a frontside of the semiconductor substrate. The insulator layer is exposed at a bottom of the TSV and an insulating liner is disposed on a sidewall of the TSV. A spacer layer is disposed conformally on the insulating liner on the sidewall and the bottom of the TSV, and a contact opening is formed through the spacer layer and the insulator layer at the bottom of TSV. The contact opening extends from the bottom of TSV through the insulator layer to a metal pad inside the insulator layer. A layer of the conductive material is deposited in the contact opening and on the sidewall of the TSV forming a vertical interconnection from the backside of the semiconductor substrate to the metal pad.

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

A high-frequency device manufacturing method is provided. The method includes providing a substrate; forming a conductive material on the substrate; standing the substrate and the conductive material for a first time duration; forming a conductive layer by sequentially repeating the steps of forming the conductive material and standing at least once; and patterning the conductive layer. The thickness of the conductive layer is in a range from 0.9 m to 10 m. A high-frequency device is also provided.

A semiconductor device includes: a frame; a first-external-terminal provided to a first side portion of the frame; a first substrate enclosed in the frame and having a first-conductive-layer at an upper surface; a first-semiconductor-element: mounted on the first-conductive-layer; having, on a lower surface, a first main electrode connecting with the first-conductive-layer; and having a second main electrode and a control electrode on an upper surface; a first terminal connecting portion establishing a connection between the first-external-terminal and an exposed portion of the first-conductive-layer between the first-semiconductor-element and the first-external-terminal; a first-external-control-terminal provided above a wire in the frame and between the first main electrode of the first-semiconductor-element and the first-external-terminal; and a first control terminal connecting portion establishing a connection: between the control electrode of the first-semiconductor-element and the first-external-control-terminal; and above a wire between the first main electrode of the first-semiconductor-element and the first-external-terminal.

Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.

A system for semiconductor wafer testing, a tangent probe card and a probe head assembly thereof. The system has a tangent probe card and a tester. Testing ends of the probe card are flat, hence the allowable alignment budget will always be more generous for the tangent probe card. The probes are held on the probe head assembly, and once the alignment is achieved accurately during manufacture, the alignment will remain stable throughout the whole life cycle. The probe has a greater CCC due to its larger cross section. The throughput of the tangent probes is higher than that of the conventional probe card since there is no need to move the pointed pin/structure. No pointed pin/structure needs to be repaired, and the flat bottom surface of the probe head assembly is easier to clean and maintain.

A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.

The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer, a spacer structure through the conductive layer and in contact with the insulating layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer. The contact structure includes a first contact portion and a second contact portion in contact with each other.

A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a structure at an edge region of the wafer to at least partially surround the inner portion of the wafer, and printing material into the inner portion of the wafer using the structure as a printing mask. A method for processing a wafer in accordance with various embodiments may include: providing a carrier and a wafer, the wafer having a first side and a second side opposite the first side, the first side of the wafer being attached to the carrier, the second side having a structure at an edge region of the wafer, the structure at least partially surrounding an inner portion of the wafer; and printing material onto at least a portion of the second side of the wafer.