Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.

To provide a sheet for sintering bonding and the same with a base material suited for lamination and integration and also suited for realizing satisfactory operational efficiency in a sintering process in a process of producing semiconductor devices that go through sintering bonding of semiconductor chips. A sheet for sintering bonding 10 of the present invention comprises an electrically conductive metal containing sinterable particle and a binder component. In this sheet, the minimum load, reached during an unloading process in load-displacement measurement according to a nanoindentation method, is −100 to −30 μN. Alternatively, the ratio of the minimum load to a maximum load, reached during a load applying process in the above measurement, is −0.2 to −0.06. A sheet body X, a sheet for sintering bonding with a base material of the present invention, has a laminated structure comprising a base material B and the sheet 10.

A conductive micro pin includes a body having a first end surface, a second end surface, a first side surface connecting the first end surface and the second end surface, and a first corner between the first end surface and the first side surface, in which the first side surface is substantially flat, and the first corner is substantially rounded.

A semiconductor package device includes a first conductive wall, a second conductive wall, a first insulation wall, a dielectric layer, a first electrode, and a second electrode. The first insulation wall is disposed between the first and second conductive walls. The dielectric layer has a first portion covering a bottom surface of the first conductive wall, a bottom surface of the second conductive wall and a bottom surface of the first insulation wall. The first electrode is electrically connected to the first conductive wall. The second electrode is electrically connected to the second conductive wall.

A semiconductor device package includes a substrate, a first circuit layer and a second circuit layer. The first circuit layer is disposed on the substrate. The first circuit layer has a plurality of dielectric layers and a first through via penetrating the dielectric layers and electrically connected to the substrate. The second circuit layer is disposed on the first circuit layer. The second circuit layer has a plurality of dielectric layers and a second through via penetrating the dielectric layers and electrically connected to the first circuit layer.

In a general aspect, a for producing a fan-out wafer level package (FOWLP) semiconductor device can include separating a semiconductor wafer into a plurality of semiconductor die and, after separating the semiconductor wafer into the plurality of semiconductor die, increasing spacing between the plurality of semiconductor die. The method can further include encapsulating, in a molding compound, the plurality of semiconductor die and determining respective locations of one or more alignment features disposed within the molding compound. The method can still further include forming, based on the determined respective locations, one or more alignment marks in the molding compound.

A method of forming an inverse opal structure along a substrate that includes depositing polymer spheres along the substrate and electroplating the substrate and spheres at a first current density to form a first solid metal layer such that the spheres are raised from the substrate. The method includes electroplating the substrate and the spheres at a second current density to diffuse metals from the substrate and deposit the metal about the spheres. The second current density is greater than the first current density. The method includes electroplating the substrate and spheres to form a second solid metal layer disposed over the spheres, and removing the spheres to form the inverse opal structure disposed between the first and second solid metal layers. The first and second solid metal layers define planar interface surfaces disposed over a porous structure of the inverse opal structure.

Structured glass articles include a glass substrate including a glass cladding layer fused to a glass core layer, a cavity formed in the glass substrate, and a shielding layer disposed within the cavity. In some embodiments, a passivation layer is disposed within the cavity such that the shielding layer is between the passivation layer and the glass substrate. A method for forming a glass fan-out includes depositing a shielding layer within a cavity in a glass substrate. The glass substrate includes a glass cladding layer fused to a glass core layer. A silicon chip may be deposited within the cavity. In some embodiments, the method also includes depositing a passivation layer within the cavity such that the shielding layer is between the passivation layer and the glass substrate.

A semiconductor device has a substrate including a terminal and an insulating layer formed over the terminal. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the insulating layer over the terminal is exposed from the encapsulant. A shielding layer is formed over the encapsulant and terminal. A portion of the shielding layer is removed to expose the portion of the insulating layer. The portion of the insulating layer is removed to expose the terminal. The portion of the shielding layer and the portion of the insulating layer can be removed by laser ablation.

A method includes etching a through-substrate via (TSV) in a substrate from a backside of the substrate. The substrate has a device layer on a frontside. The method further includes depositing a conformal spacer layer on the backside of the substrate, and sidewalls and a bottom of the TSV, and etching the spacer layer to form a self-aligned mask for etching a contact opening at the bottom of TSV to a metal pad in the device layer, and etching the contact opening at the bottom of TSV to the metal pad in the device layer. The method further includes disposing a conductive material layer in the TSV and the contact opening to make a vertical interconnection from the backside of the substrate to the metal pad in the device layer.