Disclosed is a semiconductor package including: a base substrate provided with at least one cavity and made of a metallic material; at least one semiconductor chip mounted in the cavity; and a heat dissipating member arranged in a gap between an inner surface of the cavity and the semiconductor chip.

Disclosed is a semiconductor package including: a base substrate provided with at least one cavity and made of a metallic material; at least one semiconductor chip mounted in the cavity; and a heat dissipating member arranged in a gap between an inner surface of the cavity and the semiconductor chip.

A display device according to an exemplary embodiment includes: a substrate, a thin film transistor on the substrate, a pixel electrode connected to the thin film transistor, a common electrode on the pixel electrode to be spaced apart from the pixel electrode while a plurality of microcavities are interposed between the common electrode and the pixel electrode, a roof layer on the common electrode, an alignment layer on the pixel electrode and beneath the common electrode and including a photosensitive material, a liquid crystal layer filling the microcavities, and an encapsulation layer on the roof layer to seal the microcavities.

An air cavity package includes a flange and a pedestal extending upward from the flange. A dielectric frame is joined to the flange and surrounds the pedestal. The semiconductor die is placed on the pedestal, which reduces the length of the wires joining the die to the leads of the air cavity package.

A method of selecting semiconductor chips includes: A) providing the semiconductor chips in a composite, B) producing a cohesive, mechanical first connection between the semiconductor chips and a carrier film, C) singulating the semiconductor chips, wherein the carrier film mechanically connects the semiconductor chips to one another after singulation, D) selectively weakening the first connection between some singulated semiconductor chips and the carrier film, depending on electro-optical and/or electrical properties of the semiconductor chips, and E) removing the semiconductor chips whose first connection is selectively weakened from the carrier film.

A method of selecting semiconductor chips includes: A) providing the semiconductor chips in a composite, B) producing a cohesive, mechanical first connection between the semiconductor chips and a carrier film, C) singulating the semiconductor chips, wherein the carrier film mechanically connects the semiconductor chips to one another after singulation, D) selectively weakening the first connection between some singulated semiconductor chips and the carrier film, depending on electro-optical and/or electrical properties of the semiconductor chips, and E) removing the semiconductor chips whose first connection is selectively weakened from the carrier film.

Disclosed herein is a semiconductor package in which a semiconductor chip and a mounting device are packaged together. The semiconductor package includes a semiconductor chip, a mounting block on which a first mounting device is mounted on a substrate that includes a circuit formed thereon, and an interconnection part configured to electrically connect the semiconductor chip to the mounting block.

A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

A lid array panel includes multiple lids, where each lid includes an outer side wall. The lid array panel further includes a bridge section surrounding and attached to the outer side walls of the lids, where the lids are connected to each other by the bridge section, the lid array panel further includes a reinforcement attached to the bridge section. A package structure includes a carrier, a chip disposed on an upper surface of the carrier, a lid, a bridge section, and a reinforcement. The lid includes a top wall and an outer side wall, the top wall and the outer side wall of the lid together define a cavity, and the outer side wall of the lid is attached to the upper surface of the carrier. The bridge section surrounds, and is attached to, the outer side wall of the lid. The reinforcement is attached to the bridge section.