Joining a second supporting member to one surface of a semiconductor chip through an upper layer joining portion includes: forming, on the one surface, a pre-joining layer by pressure-sintering a first constituent member containing a sintering material on the one surface such that spaces between the plurality of protrusions are filled with the pre-joining layer and the pre-joining layer has a flat surface on a side of the pre-joining layer away from the semiconductor chip; arranging, on the flat surface, the second supporting member through a second constituent member containing a sintering material; and heating and pressurizing the second constituent member. Thereby, an upper layer joining portion is formed by the second constituent member and the pre-joining layer.

A microelectronics package assembly and process of making same are disclosed. The flange has an upper surface and a first coating disposed on the upper surface of the flange. The insulator has a bottom surface for mounting onto the flange and an upper surface opposite the bottom surface. A second coating is disposed on the bottom surface of the insulator and a third coating disposed on the upper surface of the insulator. The first coating, the second coating, and the third coating each have a thickness of less than or equal to 1 micron. At least one of the first coating, the second coating, and the third coating is applied via at least one of physical vapor deposition, atomic deposition, or chemical deposition.

An integrated circuit package comprising one or more electronic component(s); a first substrate including a first surface and a second surface of the first substrate; and a second substrate including a first surface and a second surface of the second substrate. The first substrate including a first first-substrate cavity on the first surface of the first substrate. The second substrate includes a first second-substrate cavity on the first surface of the second substrate. The second surface of the first substrate and the second surface of the second substrate is located between the first surface of the first substrate and the first surface of the second substrate; or the first surface of the first substrate and the first surface of the second substrate is located between the second surface of the first substrate and the second surface of the second substrate.

An integrated circuit package comprising one or more electronic component(s); a first substrate including a first surface and a second surface of the first substrate; and a second substrate including a first surface and a second surface of the second substrate. The first substrate including a first first-substrate cavity on the first surface of the first substrate. The second substrate includes a first second-substrate cavity on the first surface of the second substrate. The second surface of the first substrate and the second surface of the second substrate is located between the first surface of the first substrate and the first surface of the second substrate; or the first surface of the first substrate and the first surface of the second substrate is located between the second surface of the first substrate and the second surface of the second substrate.

An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack.

An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack.

A mounting method for an integrated semiconductor wafer device including a glass substrate a recess, at least one semiconductor wafer that is arranged in the recess, and at least one spring element engaging in the recess for maintaining the position or orienting the semiconductor wafer, wherein the method includes providing the glass substrate with a relaxed spring element engaging in the contour space of the semiconductor wafer, providing a spring manipulator substrate with a manipulation element adapted to the contour space and/or the at least one spring element, displacing the glass substrate in relation to the spring manipulator substrate such that its manipulation element runs into the recess, placing the semiconductor wafer into the recess, and displacing the glass substrate back in relation to the spring manipulator substrate such that its manipulation element moves out of the contour space of the semiconductor wafer, releasing the spring element.

A mounting method for an integrated semiconductor wafer device including a glass substrate a recess, at least one semiconductor wafer that is arranged in the recess, and at least one spring element engaging in the recess for maintaining the position or orienting the semiconductor wafer, wherein the method includes providing the glass substrate with a relaxed spring element engaging in the contour space of the semiconductor wafer, providing a spring manipulator substrate with a manipulation element adapted to the contour space and/or the at least one spring element, displacing the glass substrate in relation to the spring manipulator substrate such that its manipulation element runs into the recess, placing the semiconductor wafer into the recess, and displacing the glass substrate back in relation to the spring manipulator substrate such that its manipulation element moves out of the contour space of the semiconductor wafer, releasing the spring element.

A semiconductor device includes: a supporting member having a wiring including a die-pad; a semiconductor element bonded to the die-pad; a wire bonded to the wiring and the semiconductor element; and a bonding layer that has a conductivity and bonds the die-pad and the semiconductor element. When viewed in a thickness direction of the semiconductor element, the die-pad includes a first region included inside a peripheral edge of the semiconductor element and a second region that is connected to the first region and extends farther then the peripheral edge of the semiconductor element. When viewed in the thickness direction, the wire is separated from the second region.

A semiconductor package includes a circuit board structure, a redistribution layer structure, a package structure, and a ring structure. The redistribution layer structure has a first region and a second region surrounding the first region. The redistribution layer structure is disposed over and electrically connected to the circuit board structure. A metal density in the second region is greater than a metal density in the first region. The package structure is disposed over the first region of the redistribution layer structure. The package structure is electrically connected to the redistribution layer structure. The ring structure is disposed over the second region of the redistribution layer structure.