Methods and apparatus for bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing substrates, includes: a first equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates, a second EFEM having one or more loadports; and a plurality of atmospheric modular mainframes (AMMs) coupled to each other and having a first AMM coupled to the first EFEM and a last AMM coupled to the second EFEM, wherein each of the plurality of AMMs include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer, and wherein the transfer chamber includes a transfer robot, the one or more process chambers, and a buffer disposed in an adjacent AMM of the plurality of AMMs.

A bonding method includes attracting and holding a first substrate by using a first holder; attracting and holding a second substrate by using a second holder; and forming a combined substrate by moving the first holder and the second holder relative to each other to bring the first substrate and the second substrate into contact with each other. The bonding method includes heating the first substrate and the second substrate or the combined substrate; and cooling the heated combined substrate by using a cooling unit. In the cooling, bending of the combined substrate is controlled by forming a temperature difference in the combined substrate.

A suction head of a pick-and-place tool for semiconductor device packaging is provided. The suction head includes: a suction unit configured to apply a suction force on a top die and pick the top die; and a warpage-correction mechanism. The warpage-correction mechanism includes a pushing mechanism, and the pushing mechanism includes a plurality of pushing units, each of the plurality of pushing units disposed in a corner region of the suction head. Each of the plurality of pushing units includes: a tubular chamber extending vertically relative to a bottom surface of the suction head; and a pusher disposed in the tubular chamber and in air-tight contact with a side wall of the tubular chamber. The pusher is movable vertically and capable of protruding out of the bottom surface of the suction head to push a corner region of the top die and apply a downward force thereon.

A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.

The present disclosure is directed to a system that uses a dual surface substrate carrier that includes a first transparent support with a first top surface and first bottom surface, a second transparent support with a second top surface and second bottom surface, and a reflective film positioned between and attached to the first transparent support and the second transparent support. The first transparent support has a first set of trenches configured in the first top surface that form a first set of ridges between the plurality of trenches and the second transparent support has a second set of trenches configured in the second top surface that form a second set of ridges between the plurality of trenches. The first transparent support is also configured with a first build surface and the second transparent support is also configured with a second build surface that are platforms for building package substrates.

A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.

A method and device for bonding a first substrate to a second substrate at contact surfaces of the substrates.

The method includes the following steps: mounting the first substrate on a first mounting surface of a first substrate holder and mounting the second substrate on a second mounting surface of a second substrate holder, wherein the substrate holders are arranged in a chamber; contacting the contact surfaces at a bond initiation surface; and bonding the first substrate to the second substrate from the bond initiation surface to the centre of the substrates.

The present disclosure provides a mothed of method of manufacturing a semiconductor device. The method includes steps of forming a dielectric layer on a substrate; etching the dielectric layer to create a plurality of openings in the dielectric layer; applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer; forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed; removing the sacrificial layer to form at least one air gap in the dielectric layer; and forming a plurality of protrusions on the bases.

An embodiment method includes providing a fan-out package structure having cavities to confine semiconductor dies by applying adhesive material which has similar coefficient of thermal expansion (CTE) with semiconductor dies in the gap between the edges of dies and the edges of cavities. The method further includes forming a molding compound over a fan-out package structure with semiconductor dies, building fan-out redistribution layers over a fan-out package structure with semiconductor dies and electrically connected to the semiconductor dies.

Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.