Patent classifications
H01L21/67155
Radiation of substrates during processing and systems thereof
A method for processing a substrate includes performing a first etch process to form a plurality of partial features in a dielectric layer disposed over the substrate; performing an irradiation process to irradiate the substrate with ultra-violet radiation having a wavelength between 100 nm and 200 nm; and after the irradiation process, performing a second etch process to form a plurality of features from the plurality of partial features.
WAFER NON-UNIFORMITY TWEAKING THROUGH LOCALIZED ION ENHANCED PLASMA (IEP)
semiconductor processing chambers include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures. The chambers may include a faceplate positioned between the blocker plate and the substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The second surface and the substrate support may at least partially define a processing region within the chamber. The faceplate may define an inner plurality of apertures. Each of the inner apertures may include a generally cylindrical aperture profile. The faceplate may define an outer plurality of apertures that are positioned radially outward from the inner apertures. Each of the outer apertures may include a conical aperture profile that extends through the second surface.
PLASMA BLOCK WITH INTEGRATED COOLING
Exemplary semiconductor processing systems may include a remote plasma source. The remote plasma source may include a first plasma block segment defining an inlet to an internal channel of the first plasma block segment. The first plasma block segment may also define a cooling channel between the internal channel of the first plasma block segment and a first exterior surface of the first plasma block segment. The remote plasma source may include a second plasma block segment defining an outlet from an internal channel of the second plasma block segment. The second plasma block segment may also define a cooling channel between the internal channel of the second plasma block segment and a first exterior surface of the second plasma block segment. The systems may include a semiconductor processing chamber defining an inlet fluidly coupled with the outlet from the remote plasma source.
MASS TRANSFER METHOD, MASS TRANSFER DEVICE AND BUFFER CARRIER
A mass transfer method, a mass transfer device and a buffer carrier are provided. The mass transfer method includes: (a) providing a plurality of electronic components disposed on a source carrier; (b) providing a buffer carrier including a plurality of adjusting cavities; and (c) transferring the electronic components from the source carrier to the buffer carrier, wherein the electronic components are placed in the adjusting cavities of the buffer carrier to adjust positions of the electronic components from shifted positions to correct positions.
System for and method of manufacture using multimodal analysis
The disclosed embodiments include systems and methods of manufacturing a product. The system may include a non-transitory computer readable medium comprising computer readable program code for performing the method. The method may include manufacturing batches of the product according to steps of a process flow, determining output data for each batch, sequencing the batches by output data, determining a plurality of modes of output data based on grouping the batches, identifying a detrimental factor to output data in a process flow step based on a correlation between the process flow step and a mode of the plurality of modes, and correcting the detrimental factor.
Vapor phase growth apparatus comprising n reactors, a primary gas supply path, a main secondary gas supply path, (n−1) auxiliary secondary gas supply paths, a first control circuit, and a second control circuit
A vapor phase growth apparatus includes n (n is an integer of 2 or more) reactors; a primary gas supply path supplying a mixed gas to the reactors; n secondary gas supply paths connected to one of the reactors including a main secondary gas supply path and (n−1) auxiliary secondary gas supply paths; a first pressure gauge; a main flow rate controller provided in the main secondary gas supply path; (n−1) auxiliary flow rate controllers provided in the auxiliary secondary gas supply paths; a first control circuit instructing a first flow rate value; and a second control circuit calculating a second flow rate value being 1/n of a sum of a flow rate value measured by the main flow rate controller and flow rate values measured by the auxiliary flow rate controllers, and instructing the second flow rate value to the auxiliary flow rate controllers.
BOTTOM PURGE FOR SEMICONDUCTOR PROCESSING SYSTEM
Exemplary substrate processing systems may include a plurality of processing regions. The systems may include a transfer region housing defining a transfer region fluidly coupled with the plurality of processing regions. The systems may include a plurality of substrate supports, and each substrate support of the plurality of substrate supports may be vertically translatable between the transfer region and an associated processing region of the plurality of processing regions. The systems may include a transfer apparatus including a rotatable shaft extending through the transfer region housing. The transfer apparatus may include an end effector coupled with the rotatable shaft. The end effector may include a central hub defining a central aperture fluidly coupled with a purge source. The end effector may also include a plurality of arms having a number of arms equal to a number of substrate supports of the plurality of substrate supports.
APPARATUS AND METHODS FOR MANIPULATING POWER AT AN EDGE RING IN A PLASMA PROCESSING DEVICE
Methods and apparatus for processing a substrate positioned on a substrate support assembly are provided. For example, a substrate support assembly includes an electrostatic chuck having one or more chucking electrodes embedded therein for chucking a substrate to a substrate support surface of the electrostatic chuck; an edge ring disposed on the electrostatic chuck and surrounding the substrate support strike; two or more radio frequency (RF) power sources coupled to the edge ring and at least one of a baseplate disposed beneath the electrostatic chuck or an electrode disposed in the electrostatic chuck; a matching network coupling the edge ring to the two or more RF power sources; and an RF circuit coupling the edge ring to the two or more RF power sources, the RF circuit configured to simultaneously tune at least one of an RF amplitude or an RF phase of respective signals of the two or more RF power sources.
COVALENTLY BONDED SEMICONDUCTOR INTERFACES
Production system for wafer bonding comprising modules for wet chemical wafer cleaning and surface passivation and vacuum modules with base pressure in the ultrahigh vacuum regime for the removal of surface passivation, wafer flipping and alignment, low temperature annealing and wafer bonding, with all modules integrated in the same tool and individually serviceable. Methods for oxide-free covalent semiconductor wafer bonding include wet chemistry and vacuum processing at low temperatures compatible with CMOS processed wafers.
Shutter monitoring system
The present disclosure is directed to a method and system for monitoring a distance between a shutter and a reference point in a processing module. For example, the method includes moving a shutter relative to a substrate support in a wafer processing module and determining a distance between the shutter and a wall of the wafer processing module with a measurement device. In response to the distance being greater than a value, the method further includes transferring a substrate to the substrate support, and in response to the distance being equal to or less than the value, the method includes resetting the shutter.