A semiconductor fabrication scheduling method includes creating a load scheduling data schema including facility data of product lots to be dispatched to a plurality of workstations; generating a load schedule profile using a load-balancing model and based on the load scheduling data schema, wherein the load-balancing model includes one or more objective functions and there is at least one weight factor in an objective function; generating a current load schedule based on the load schedule profile; dispatching the product lots to the plurality of workstations using the current load schedule to complete fabrication of the product lots; obtaining a set of current key performance indicators (KPIs) of the completed fabrication of the product lots; and automatically adjusting the weight factors of the objective functions of the load-balancing model based on the current KPIs using a big-data architecture to generate a next load schedule for next cycle of fabrication.

In accordance with some embodiments, a method for processing a semiconductor wafer is provided. The method includes transporting a carrier along with a reticle supported by the carrier in a lithography exposure apparatus. The method also includes regulating particles in the carrier through a magnetic field. In addition, the method includes removing the reticle from the carrier. The method further includes performing, using the reticle, a lithography exposure process to the semiconductor wafer in the lithography exposure apparatus.

Systems and methods are described for depositing a TiN liner layer and a cobalt seed layer on a semiconductor wafer in a cobalt metallization process. In some embodiments the wafer is cooled after deposition of the TiN liner layer and/or the cobalt seed layer. In some embodiments the TiN liner layer and cobalt seed layer are deposited in process modules that are part of a semiconductor processing apparatus that also includes one or more modules for cooling the substrate. In some embodiments the cobalt seed layer may comprise a mixture of TiN and cobalt, a nanolaminate of TiN and cobalt layers or a graded TiN/Co layer.

In accordance with some embodiments, a method for processing a semiconductor wafer is provided. The method includes transporting a carrier along with a reticle supported by the carrier in a lithography exposure apparatus. The method also includes regulating particles in the carrier through a magnetic field. In addition, the method includes removing the reticle from the carrier. The method further includes performing, using the reticle, a lithography exposure process to the semiconductor wafer in the lithography exposure apparatus.

Disclosed is an apparatus and method of processing substrate, which facilitates to improve deposition uniformity of a thin film deposited on a substrate, and to control quality of a thin film, wherein the apparatus includes a process chamber; a substrate supporter for supporting at least one of substrates, wherein the substrate supporter is provided in the bottom of the process chamber; a chamber lid confronting the substrate supporter, the chamber lid for covering an upper side of the process chamber; and a gas distributor for locally distributing activated source gas on the substrate, wherein the gas distributor locally confronting the substrate supporter is provided in the chamber lid, wherein the gas distributor forms plasma by the use of plasma formation gas, and activates the source gas by distributing the source gas to some of plasma area for formation of the plasma.

A method includes identifying first parameters of a first processing chamber of a semiconductor fabrication facility. The first parameters include first input parameters and first output parameters. The method further includes identifying second parameters of a second processing chamber of the semiconductor fabrication facility. The second parameters include second input parameters and second output parameters. The method further includes generating, by a processing device based on the first parameters and the second parameters, composite parameters comprising composite input parameters and composite output parameters. Semiconductor fabrication is based on the composite parameters.

Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

An apparatus for processing a substrate may include a mixture bath, a plurality of reaction chambers and a control module. The mixture bath may be configured to receive a plurality of chemicals to form a mixture. Each of the reaction chambers may be configured to receive a respective substrate of a plurality of the substrates to be processed by the mixture. The control module may be configured to control supply of the mixture supplied from the mixing bath to the reaction chambers with a uniform concentration.

There is provided a substrate processing method which includes: treating a substrate using a fluorine-containing gas; and exposing the substrate to a moisture-containing atmosphere.

An apparatus including a drive; and a movable arm assembly connected to the drive. The movable arm assembly includes a first arm and a second arm, where the first arm includes a first upper arm, a first forearm and a first end effector, and where the second arm includes a second upper arm, a second forearm and a second end effector. The first end effector includes at least two first substrate holding areas. The second end effector includes at least two second substrate holding areas. The drive and the movable arm assembly are configured to prevent the movable arm assembly from passing over top sides of substrates located on the first and second substrate holding areas.