In certain embodiments, a system includes: a source lane configured to move a first die container between a load port and a source lane staging area; an inspection sensor configured to produce a sensor result based on a die on the first die container; a pass target lane configured to move a second die container between a pass target lane out port and a pass target lane staging area; a fail target lane configured to move a third die container between a fail target lane out port and a fail target lane staging area; and a conveyor configured to move the die from the first die container at the source lane staging area to either the second die container at the pass target lane staging area or the fail target lane staging area based on the sensor result.

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler. The control patterns may be part of a library of control patterns.

A die sorter tool may include a first conveyor, and a first lane to receive, from one or more load ports and via the first conveyor, a carrier with a set of dies. The die sorter tool may include a die flip module to receive the carrier from the first lane, manipulate one or more dies of the set of dies by changing orientations of the one or more dies, and return the one or more dies to the carrier after manipulating the one or more dies and without changing positions of the one or more dies within the carrier. The die sorter tool may include a second conveyor, and a second lane to receive, via the second conveyor, the carrier from the die flip module, and provide, via the first conveyor, the carrier to the one or more load ports.

A substrate rotator configured to rotate one or more substrates includes a body, a body actuator coupled to the body and configured to rotate the body, and a first and second gripper coupled to the body. A substrate edge metrology system that measures side chips or other defects on all sides of the substrate is also described. The metrology system includes two metrology stations and the substrate rotator. Methods for measuring side chips or other defects on a substrate are also provided. The method includes performing metrology on a first set of sides of the first substrate, rotating the first substrate by a first angle, and performing metrology on the second set of sides of the first substrate.

Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax. The chips are sorted into different process windows, based on the voltage identified.

A method for preparing a plurality of micro-devices for transfer includes temporarily bonding the micro-devices onto a carrier substrate; testing the micro-devices on the carrier substrate to determine if there is at least one first failed micro-device in the micro-devices; and removing the first failed micro-device from the carrier substrate.

A system for depositing one or more layers, particularly layers including organic materials therein, is described. The system includes a load lock chamber for loading a substrate to be processed, a transfer chamber for transporting the substrate, a vacuum swing module provided between the load lock chamber and the transfer chamber, at least one deposition apparatus for depositing material in a vacuum chamber of the at least one deposition chamber, wherein the at least one deposition apparatus is connected to the transfer chamber; a further load lock chamber for unloading the substrate that has been processed, a further transfer chamber for transporting the substrate, a further vacuum swing module provided between the further load lock chamber and the further transfer chamber, and a carrier return track from the further vacuum swing module to the vacuum swing module, wherein the carrier return track is configured to transport the carrier under vacuum conditions and/or under a controlled inert atmosphere.

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler. The control patterns may be part of a library of control patterns.

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause phototransistors or electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler. A set of micro-object may be analyzed. Geometric properties of the set of micro-objects may be identified. The set of micro-objects may be divided into multiple sub-sets of micro-objects based on the one or more geometric properties and one or more control patterns.