A method of detecting adhesive residue on a wafer after peeling an adhesive film from the wafer by using a peeling tape is described. According to a first aspect, the method includes illuminating the peeling tape with first UV light after the peeling and acquiring a fluorescence image from the peeling tape. According to a second aspect, the method includes illuminating the wafer with second UV light after the peeling and acquiring a fluorescence image from the wafer.

An inspection system includes a laser light source, an optical system for laser marking that irradiates a semiconductor device with laser light from a metal layer side, a control unit that controls the laser light source to control laser marking, a two-dimensional camera that detects light from the semiconductor device on a substrate side and outputs an optical reflection image, and an analysis unit that generates a pattern image of the semiconductor device, and the control unit controls the laser light source so that laser marking is performed until a mark image appears in a pattern image.

Disclosed herein are implementations of a particles-transferring system, particle transferring unit, and method of transferring particles in a pattern. In one implementation, a particles-transferring system includes a first substrate including a first surface to support particles in a pattern, particle transferring unit including an outer surface to be offset from the first surface by a first gap, and second substrate including a second surface to be offset from the outer surface by a second gap. The particle transferring unit removes the particles from the first surface in response to the particles being within the first gap, secures the particles in the pattern to the outer surface, and transports the particles in the pattern. The second substrate removes the particles in the pattern from the particle transferring unit in response to the particles being within the second gap. The particles are to be secured in the pattern to the second surface.

Methods and systems for tracking an edge ring includes capturing an edge ring identifier from a source related to the edge ring. The edge ring is inserted into a slot of an edge ring carrier, wherein the edge ring is being assigned to the edge ring carrier. The edge ring identifier is tracked to determine transfers into and out of the edge ring carrier and into and out of a processing station. The tracking of the edge ring identifier builds a metadata file that provides lifetime information regarding the edge ring.

Verifying a semiconductor product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

A method includes measuring a topography of a semiconductor wafer. A distortion function is generated based on the measured topography. Measured alignment data associated with the semiconductor wafer is adjusted using the distortion function. At least one correction factor for an exposure tool is generated based on the adjusted alignment data. The exposure tool is configured based on the at least one correction factor.

A substrate structure includes at least one detachable first substrate unit and a substrate body. The detachable first substrate unit includes a plurality of corners and a plurality of first engagement portions. Each of the first engagement portions is disposed at each of the corners of the detachable first substrate unit. The substrate body includes a plurality of second substrate units, at least one opening and a plurality of second engagement portions. The opening is substantially defined by a plurality of sidewalls of the second substrate units, and includes a plurality of corners. Each of the second engagement portions is disposed at each of the corners of the opening. The detachable first substrate unit is disposed in the opening, and the second engagement portions are engaged with the first engagement portions.

The present disclosure describes a method for controlling a wet processing system includes dispensing one or more chemicals into a processing chamber according to one or more process parameters. The method also includes injecting one or more illumination markers into the processing chamber and obtaining images representing locations of the one or more illumination markers. The method further includes determining a trajectory of an illumination marker of the one or more illumination markers based on the images and determining whether the determined trajectory is outside a predetermined trajectory range. In response to the determined trajectory being outside the predetermined trajectory range, the method further includes adjusting the one or more process parameters.

A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.

The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.