H01L21/67288

SEMICONDUCTOR CLEANING APPARATUS AND METHOD

The present disclosure describes a chuck-based device and a method for cleaning a semiconductor manufacturing system. The semiconductor manufacturing system can include a chamber, a chuck housed in the chamber and configured to hold a substrate, and a control device configured to control a translational displacement and a rotation of the chuck. The chuck can include a passage extending along a periphery of the chuck and dividing the chuck into an inner portion and an outer sidewall portion, and a first multiple of openings through the outer sidewall portion of the chuck and interconnected with the passage. The passage can be configured to transport a fluid. The first multiple of openings can be configured to dispense the fluid.

METHOD AND SYSTEM FOR RECOGNIZING AND ADDRESSING PLASMA DISCHARGE DURING SEMICONDUCTOR PROCESSES
20220359244 · 2022-11-10 ·

A plasma discharge detection system detects undesirable plasma discharge events within a semiconductor process chamber. The plasma discharge detection system includes one or more cameras positioned around the semiconductor process chamber. The cameras capture images from within the semiconductor process chamber. The plasma discharge detection system includes a control system that receives the images from the cameras. The control system analyzes the images and detects plasma discharge within the semiconductor process chamber based on the images. The control system can adjust a semiconductor process in real time responsive to detecting the plasma discharge.

SYSTEMS AND METHODS FOR SEMICONDUCTOR ADAPTIVE TESTING USING INLINE DEFECT PART AVERAGE TESTING

Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.

Device and method for cleaning a printing device
11575064 · 2023-02-07 · ·

An apparatus for producing semiconductor cells, the apparatus comprises a printing device for printing on a semiconductor cell, a monitoring device configured to monitor characteristics of the printed semiconductor cell, and a cleaning device configured for cleaning at least one part of the printing device based on the monitored characteristics of the semiconductor cells.

Automated Fault Detection in Microfabrication
20220351997 · 2022-11-03 ·

A method including: collecting first processing tool machine data from a first processing tool while treating semiconductor substrates, the first processing tool machine data including process data and operational codes associated with one or more discrete intervals of time during the treatments, training a first neural network with the first processing tool machine data from the first processing tool, and generating a first output indicative of a fault of the first processing tool from the first neural network, based, at least in part, on applying subsequent machine data from at least one processing tool.

SYSTEM AND METHOD FOR MITIGATING OVERLAY DISTORTION PATTERNS CAUSED BY A WAFER BONDING TOOL
20230035201 · 2023-02-02 ·

A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.

Methods and systems for product failure prediction based on X-ray image re-examination

In one embodiment, an X-ray inspection system may access a first set of X-ray images of one or more first samples that are labeled as being non-conforming. The system may adjust a classification algorithm based on the first set of X-ray images. The classification algorithm may classify samples into conforming or non-conforming categories based on an analysis of corresponding X-ray images. The system may analyze a second set of X-ray images of a number of second samples using the adjusted classification algorithm. The second samples may be previously inspected samples that have been classified as conforming by the classification algorithm during a previous analysis before the classification algorithm is adjusted. The system may identify one or more of the second samples from the second set of X-ray images. Each identified second sample may be classified as non-conforming by the adjusted classification algorithm.

SYSTEM AND METHOD FOR OPTIMIZING THROUGH SILICON VIA OVERLAY
20230030116 · 2023-02-02 ·

A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform stress-free shape measurements on an active wafer, a carrier wafer, and a bonded device wafer. The active wafer includes functioning logic circuitry and the carrier wafer is electrically passive. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements; determine overlay distortion between features on the active wafer and the carrier wafer; and convert the overlay distortion to a feed-forward correction for one or more lithographic scanners. The controller is also configured to determine a control range for a bonder or lithography scanner; predict an overlay distortion pattern; calculate an optimal control signature based on a minimal achievable overlay; and provide a feed-forward correction to the bonder or lithography scanner based on the calculated optimal control signature.

Integrated semiconductor die vessel processing workstations

In certain embodiments, a workstation includes: a cleaning station configured to clean a die vessel, wherein the die vessel is configured to secure a semiconductor die; an inspection station configured to inspect the die vessel after cleaning to determine whether the die vessel is identified as passing inspection; and a conveyor configured to move the die vessel between the cleaning station and the inspection station.

Substrate inspection method and method of fabricating a semiconductor device using the same

Disclosed are a substrate inspection method and a method of fabricating a semiconductor device using the same. The inspection method may include measuring a target area of a substrate using a pulsed beam to obtain a first peak, measuring a near field ultrasound, which is produced by the pulsed beam in a near field region including the target area, using a first continuous wave beam different from the pulsed beam to obtain a second peak, and measuring a far field ultrasound, which is produced by the near field ultrasound in a far field region outside the near field region, using a second continuous wave beam to examine material characteristics of the substrate.