The present disclosure provides a manufacturing method for semiconductor structures. The method includes the following operations: receiving a wafer having a plurality of dies; respectively forming a plurality of semiconductor structures in a plurality of banks in each of the plurality of dies, wherein each of the semiconductor structure includes a first fin array and a second fin array disposed above the first fin array; performing a PWG measurement on the wafer to obtain a displacement between a first fin of the first fin array and a first fin of the second fin array; and according to the displacement, determining a status of wafer.

A testing apparatus for measuring a strength of a chip includes: a cassette mounting base on which to mount a cassette capable of accommodating wafer units; a frame fixing mechanism that fixes an annular frame of the wafer unit; a conveying mechanism that conveys the wafer unit between the cassette and the frame fixing mechanism; a pushing-up mechanism that pushes up a predetermined chip included in the wafer supported by the annular frame fixed by the frame fixing mechanism; a pick-up mechanism having a collet picking up the chip pushed up by the pushing-up mechanism; a strength measuring mechanism having a support unit supporting the chip picked up by the collet; and a collet moving mechanism that moves the collect from a position facing the pushing-up mechanism to a position facing the support unit.

Metrology targets and methods are provided, which comprise at least two overlapping structures configured to be measurable in a mutually exclusive manner at least at two different corresponding optical conditions. The targets may be single cell targets which are measured at different optical conditions which enable independent measurements of the different layers of the target. Accordingly, the targets may be designed to be very small, and be located in-die for providing accurate metrology measured of complex devices.

According to an aspect of the present disclosure, a substrate state determining apparatus includes: an image capturing unit that captures an image of a substrate placed on a stage; a learning unit that executes a machine learning using training data in which information indicating a state of the substrate is attached to the image of the substrate, so as to generate a substrate state determination model in which the image of the substrate is taken as an input and a value related to the state of the substrate corresponding to the image of the substrate is taken as an output; and a determination unit that determines the state of the substrate corresponding to the image of the substrate captured by the image capturing unit, using the substrate state determination model generated by the learning unit.

Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

A semiconductor device includes a substrate and a semiconductor layer. The substrate includes a planar portion and a plurality of pillars on a periphery of the planar portion. The pillars are shaped as rectangular columns, and corners of two of the pillars at the same side of the planar portion are aligned in a horizontal direction or a direction perpendicular to the horizontal direction. The semiconductor layer is disposed over the planar portion and between the pillars.

A method for process control in the manufacture of semiconductor devices including performing metrology on at least one Design of Experiment (DOE) semiconductor wafer included in a lot of semiconductor wafers, the lot forming part of a batch of semiconductor wafer lots, generating, based on the metrology, one or more correctables to a process used to manufacture the lot of semiconductor wafers and adjusting, based on the correctables, the process performed on at least one of; other semiconductor wafers included in the lot of semi-conductor wafers, and other lots of semiconductor wafers included in the batch.

A semiconductor review tool receives absolute Z-height values for the semiconductor wafer, such as a semiconductor wafer with a beveled edge. The absolute Z-height values can be determined by a semiconductor inspection tool. The semiconductor review tool reviews the semiconductor wafer within a Z-height based on the absolute Z-height values. Focus can be adjusted to within the Z-height.

An information processing method includes obtaining information on a deformation factor of a surface of a target substrate; obtaining a surface image of the target substrate; calculating a correction coefficient for correcting an image change due to deformation of the surface, based on the information on the deformation factor of the surface; and generating a corrected image of the target substrate by correcting the surface image of the target substrate using the correction coefficient.

A cleaning method applied in semiconductor manufacturing is provided. The method includes: receiving a substrate having a surface; identifying a location of a particle on the surface of the substrate; moving a cleaning apparatus toward the location of the particle; performing a cleaning operation, thereby removing the particle by spraying a cleaning liquid from the cleaning apparatus flowing against gravity and toward the surface of the substrate; detecting the surface of the substrate; and performing a second cleaning operation when a cleaning result of the detection is not acceptable. A semiconductor manufacturing method and a system for cleaning a substrate are also provided.