A semiconductor package includes a substrate, at least one semiconductor chip arranged in the substrate and having chip pads, and a redistribution wiring layer covering a lower surface of the substrate and including first and second redistribution wirings and dummy patterns, the first and second redistribution wirings being stacked in at least two levels and connected to the chip pads. The first and second redistribution wirings are arranged in a redistribution region of the redistribution wiring layer, and the dummy patterns extend in an outer region outside the redistribution region to partially cover corner portions of the redistribution wiring layer, respectively.

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.

A protective sheeting for use in processing a semiconductor-sized wafer has a substantially circular base sheet and a substantially annular adhesive layer applied to a peripheral portion of a first surface of the base sheet. The inner diameter of the adhesive layer is smaller than the diameter of the wafer. Further, the outer diameter of the adhesive layer is larger than the inner diameter of an annular frame for holding the wafer. A related method includes attaching the protective sheeting to a front side or a back side of the wafer via the adhesive layer on the first surface of the base sheet so that an inner peripheral portion of the adhesive layer adheres to an outer peripheral portion of the front side or the back side of the wafer, and processing the wafer after the protective sheeting has been attached to the front side or the back side thereof.

The invention comprises a butyl acetate-silicone formulation comprising (A) an organopolysiloxane containing an average of at least two silicon-bonded alkenyl groups per molecule, (B) an organosilicon compound containing an average of at least two silicon-bonded hydrogen atoms per molecule; (C) a hydrosilylation catalyst; and a coating effective amount of (D) butyl acetate. The invention also comprises related silicone formulations made by removing a portion, or all, of (D) butyl acetate therefrom, and related cured products, methods, articles and devices.

Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

A method is for detecting a condition associated with a final phase of a plasma dicing process. The method includes providing a non-metallic substrate having a plurality of dicing lanes defined thereon, plasma etching through the substrate along the dicing lanes, wherein during the plasma etching infrared emission emanating from at least a portion of the dicing lanes is monitored so that an increase in infrared emission from the dicing lanes is observed as the final phase of the plasma dicing operation is entered, and detecting the condition associated with the final phase of the plasma dicing from the monitored infrared emission.

A method of processing a semiconductor wafer, in which a mask is formed: by cutting, with CO.sub.2 laser, a portion corresponding to a street, out of a temporary-adhesive of a surface protective tape to protect on a patterned face; carrying out dicing with SF.sub.6 plasma; and carrying out ashing, by removing a layer of the temporary-adhesive, with O.sub.2 plasma; a semiconductor chip; and a surface protective tape.

A wafer-fixing tape, having: an temporary-adhesive layer provided on a substrate film, wherein the substrate film contains an ionomer resin comprising a terpolymer crosslinked by a metal ion, and wherein an arithmetic average roughness Ra of a surface of the substrate film opposite to the temporary-adhesive layer 5b is from 0.1 to 3.0 μm; a processing method of a semiconductor wafer; and a semiconductor chip.

A semiconductor package is disclosed. The semiconductor package includes a substrate with a first surface, a second surface and sidewalls. The package also includes backside metallization (BSM) over the second surface of the substrate. The semiconductor package is devoid of metal debris.

A mask-integrated surface protective tape, containing: a substrate film; a temporary-adhesive layer provided on the substrate film; and a mask material layer provided on the temporary-adhesive layer; wherein the mask material layer and the temporary-adhesive layer each contain a (meth)acrylic copolymer; and wherein the mask-integrated surface protective tape is used for a method of producing a semiconductor chip utilizing a plasma-dicing.