A semiconductor device includes: a SiC substrate; a device structure in or on the SiC substrate and subject to an electric field during operation of the semiconductor device; a current-conduction region of a first conductivity type in the SiC substrate adjoining the device structure; and a shielding region of a second conductivity type laterally adjacent to the current-conduction region and configured to at least partly shield the device structure from the electric field. The shielding region has a higher net doping concentration than the current-conduction region, and has a length (L) measured from a first position which corresponds to a bottom of the device structure to a second position which corresponds to a bottom of the shielding region. The current-conduction region has a width (d) measured between opposing lateral sides of the current-conduction region, and L/d is in a range of 1 to 10.

Provided is a SiC substrate treatment method for, with respect to a SiC substrate (40) that has, on its surface, grooves (41), activating ions while preventing roughening of the surface of the substrate. In the method, an ion activation treatment in which the SiC substrate (40) is heated under Si vapor pressure is performed to the SiC substrate (40) has, on its surface, an ion implantation region (46) in which ions have been implanted, and has the grooves (41) provided in a region including at least the ion implantation region (46), thereby ions that are implanted in the SiC substrate (40) is activated while etching the surface of the substrate.

A power semiconductor device is described. The device comprises a silicon carbide substrate and a layer of monocrystalline silicon having a thickness t.sub.Si no more than 5 m disposed directly on the substrate or directly on an interfacial layer having a thickness no more than 100 nm which is disposed directly on the substrate. The device comprises a lateral transistor, such as a laterally-diffused metal oxide semiconductor transistor or lateral insulated gate bipolar transistor, comprising first and second contacts laterally-spaced contact regions disposed in the monocrystalline silicon layer.

To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.

A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

Fabrication methods and structures for forming integrated circuit (IC) porous semiconductor (-Semi) isolation structures such as shallow trench isolation (STI) and/or deep trench isolation (DTI) structures. The methods speed up IC front-end-of-line processing and decrease the cost of IC fabrication. In general, exposed portions of a semiconductor layer are subjected to an electrochemical etching to form -Semi isolation structures; in essence, the in situ semiconductor is restructured to -Semi. The characteristics of -Semi, particularly mesoporous -Semi and microporous -Semi, include good electrical insulation as well as hole trapping capability. Accordingly, -Semi used for STI and/or DTI structures provides excellent electrical isolation. A first embodiment comprises a pre-FET -Semi isolation structure, fabricated before formation of gate, drain, and source structures or regions of a field-effect transistor (FET). A second embodiment comprises a post-FET -Semi isolation structure, fabricated after formation of gate, drain, and source structures or regions of a FET.

A semiconductor device includes: metal collector layer on backside, P-type collector layer, N-type field stop layer and N drift layer. There are active cells and dummy cells on top of the device. The active cell and dummy cell are separated by gate trench. The gate trench is formed by polysilicon and gate oxide layer. There are N+ region and P+ region in active cells, and they are connected to metal emitter layer through the window in the insulation layer. There are P-well regions in both active cells and dummy cells. The P-well regions in active cells are continuous and connected to emitter electrode through P+ region. The P-well regions in dummy cells are discontinuous and electrically floating.

A silicon carbide semiconductor device includes an electric field relaxation layer disposed in a drift layer. The electric field relaxation layer includes a first region having a second conductivity type and disposed at a position deeper than trenches, and a second region having the second conductivity type and disposed between the adjacent trenches to be away from a side surface of each of the adjacent trenches. Each of the first region and the second region is made of an ion implantation layer. The electric field relaxation layer further includes a double implantation region in which the first region and the second region overlap with each other, and the electric field relaxation layer has a peak of a second conductivity type impurity concentration in the double implantation region.

The present application discloses an SiC MOSFET device, including an SiC epitaxial layer in which a trench gate is formed, wherein a first bottom doped region is formed below a bottom surface of a gate trench, a second deep doped region with spacing from the gate trench is formed in the SiC epitaxial layer, the first bottom doped region is connected to a source so that voltage borne by a gate dielectric layer on the bottom surface of the gate trench is determined by gate-source voltage; the second deep doped region extends downward from a top surface of the SiC epitaxial layer, and a bottom surface of the second deep doped region is located below a bottom surface of the first bottom doped region; a top of the second deep doped region is connected to the source. The present application further discloses a method for manufacturing an SiC MOSFET device.