A silicon carbide semiconductor device includes, on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first semiconductor region of the first conductivity type selectively provided on a first side of the third semiconductor layer opposite to a second side thereof facing the silicon carbide semiconductor substrate, second semiconductor regions of the second conductivity type that have an impurity concentration higher than that of the second semiconductor layer, trenches, gate electrodes provided via gate insulating films, an interlayer insulating film, a first electrode, and a second electrode. The first semiconductor region is thinner than a portion of the third semiconductor layer between the first semiconductor region and the second semiconductor layer.

A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

A method to make a semiconductor device, a first SiO.sub.2 layer and a first Si.sub.3N.sub.4 layer are sequentially formed on the semiconductor substrate. The first SiO.sub.2 layer and the first Si.sub.3N.sub.4 layer are then patterned as etching mask to form a trench in a semiconductor substrate by a trench etching process. After this, a second SiO.sub.2 layer and a second Si.sub.3N.sub.4 layer are formed conformal onto the substrate. Anisotropic etching is then performed to remove the second Si.sub.3N.sub.4 and second SiO.sub.2 layer except on the trench sidewall. Then a thermal oxidation process is done to grow oxide only in trench bottom and at trench top corner. The radius of curvature of trench bottom and trench top corner is increased at the same time by this thermal oxidation process.

In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

A silicon carbide semiconductor device includes an electric field relaxation layer disposed in a drift layer. The electric field relaxation layer includes a first region having a second conductivity type and disposed at a position deeper than trenches, and a second region having the second conductivity type and disposed between the adjacent trenches to be away from a side surface of each of the adjacent trenches. Each of the first region and the second region is made of an ion implantation layer. The electric field relaxation layer further includes a double implantation region in which the first region and the second region overlap with each other, and the electric field relaxation layer has a peak of a second conductivity type impurity concentration in the double implantation region.

Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate including a plurality of active areas and first isolation structures arranged at intervals along a first direction; gate structures located in the active areas and the first isolation structures. Top surfaces of the active areas extend beyond top surfaces of the gate structures; second isolation structures with a preset height located on surfaces of the gate structures, and the top surfaces of the second isolation structures are flush with the top surfaces of the active areas.

P-type low-concentration regions face bottoms of trenches and extend in a longitudinal direction (first direction) of the trenches. The p-type low-concentration regions are adjacent to one another in a latitudinal direction (second direction) of the trenches and connected at predetermined locations by p-type low-concentration connecting portions that are scattered along the first direction and separated from one another by an interval of at least 3 m. The p-type low-concentration regions and the p-type low-concentration connecting portions have an impurity concentration in a range of 310.sup.17/cm.sup.3 to 910.sup.17/cm.sup.3. A depth from the bottoms of the trenches to lower surfaces of the p-type low-concentration regions is in a range of 0.7 m to 1.1 m. Between the bottom of each of the trenches and a respective one of the p-type low-concentration regions, a p.sup.+-type high-concentration region is provided. Each p.sup.+-type high-concentration region has an impurity concentration that is at least 2 times the impurity concentration of the p-type low-concentration regions.

A semiconductor device includes: a high-concentration layer of a first conductivity-type provided on a drift layer of the first conductivity-type; a buried layer of a second conductivity-type provided in the high-concentration layer; an injection regulation region of the second conductivity-type provided on the high-concentration layer; a high-concentration region of the second conductivity-type provided inside the injection regulation region; a carrier supply region of the first conductivity-type provided at an upper part of the injection regulation region; and an insulated gate structure provided inside a trench, wherein a ratio of the impurity concentration of the injection regulation region to an impurity concentration of an upper part of the high-concentration layer is 0.5 or greater and 2 or smaller.

The present disclose relates to a SiC MOSFET device and a manufacturing method thereof. The method includes providing a semiconductor base of a first doping type; forming a patterned first barrier layer on an upper surface; forming a source region extending from the upper surface to the interior of the semiconductor base by taking the first barrier layer as a mask, wherein the source region is of the first doping type; etching a part of the first barrier layer to form a second barrier layer, and allowing anion implantation window of the second barrier layer to be larger than the ion implantation window of the first barrier layer; forming a first type base region by taking the second barrier layer as a mask, wherein the first type base region is of a second doping type; and forming a contact region of the second doping type.