Method of forming a trench in a semiconductor device

Abstract

A method to make a semiconductor device, a first SiO.sub.2 layer and a first Si.sub.3N.sub.4 layer are sequentially formed on the semiconductor substrate. The first SiO.sub.2 layer and the first Si.sub.3N.sub.4 layer are then patterned as etching mask to form a trench in a semiconductor substrate by a trench etching process. After this, a second SiO.sub.2 layer and a second Si.sub.3N.sub.4 layer are formed conformal onto the substrate. Anisotropic etching is then performed to remove the second Si.sub.3N.sub.4 and second SiO.sub.2 layer except on the trench sidewall. Then a thermal oxidation process is done to grow oxide only in trench bottom and at trench top corner. The radius of curvature of trench bottom and trench top corner is increased at the same time by this thermal oxidation process.

Claims

1. A method of forming a trench in a semi-conductor substrate, the method comprising the steps of: a) providing a semiconductor substrate with a planar surface with a first SiO2 layer disposed on the planar surface thereof, and a first Si3N4 layer on the first SiO2 layer, b) patterning the first SiO2 layer and the first Si3N4 layer by lithography and etching; c) etching a trench into the substrate using the first SiO2 layer and a first Si3N4 layer as an etching mask; d) depositing a second SiO2 conformal layer on the side of the substrate having the trench, e) depositing a second Si3N4 conformal layer on the side of the substrate having the trench, f) anisotropically etching the side of the substrate having the trench to remove the second Si3N4 layer and the second SiO2 layer on substrate surfaces that are parallel to the planar substrate surface wherein the trench sidewall retain at least a portion of the second Si3N4 layer and the second SiO2 layer, g) thermally oxidizing the side of the substrate having the trench to an extent necessary to grow thermal oxide in a trench bottom and at a trench top corner; h) removing all Si3N4 layers and SiO2 layers.

2. The method of claim 1, wherein the semiconductor substrate material is selected from the group consisting of silicon and silicon carbide.

3. The method of claim 1 wherein said step of anisotropically etching the side of the substrate having the trench to remove the second Si3N4 layer and the second SiO2 layer on substrate surfaces that are parallel to the planar substrate surface provides for the entire trench sidewalls to remain protected from oxidation in step g) by the second Si3N4 layer and the second SiO2 layer.

4. The method of claim 1 wherein said step of anisotropically etching the side of the substrate having the trench to remove the second Si3N4 layer and the second SiO2 layer on substrate surfaces that are parallel to the planar substrate surface exposes a junction of the first and second SiO2 layers.

5. The method of claim 1 wherein said step g) of thermally oxidizing the side of the substrate having the trench to an extent necessary to grow thermal oxide in a trench bottom and at a trench top corner occurs after said step f) of anisotropically etching the side of the substrate having the trench to remove the second Si3N4 layer and the second SiO2 layer on substrate surfaces that are parallel to the planar substrate surface wherein the trench sidewall retain at least a portion of the second Si3N4 layer and the second SiO2 layer.

6. The method of claim 1 wherein said step g) of thermally oxidizing the side of the substrate having the trench to an extent necessary to grow thermal oxide in a trench bottom and at a trench top corner occurs immediately after said step f) of anisotropically etching the side of the substrate having the trench to remove the second Si3N4 layer and the second SiO2 layer on substrate surfaces that are parallel to the planar substrate surface wherein the trench sidewall retain at least a portion of the second Si3N4 layer and the second SiO2 layer.

7. The method of claim 1 wherein said step of etching a trench into the substrate using the first SiO2 layer and a first Si3N4 layer as an etching mask form a round bottom of the resulting trench.

8. The method of claim 7 wherein said step of etching a trench into the substrate using the first SiO2 layer and a first Si3N4 layer as an etching mask form a trench with a bottom having radius that half the width of the trench.

9. The method of claim 1 wherein substrate is silicon and the silicon at a trench corner is consumed by growing SiO2 in step g) causing the first Si3N4 layer at the trench corner to lift away from first Si3N4 layer on the trench sidewalls.

10. The method of claim 1 wherein the step of thermally oxidizing in step g) expand the trench radius by at least about 50%.

11. The method of claim 1 wherein the resulting trench has a depth of about 5 microns and a width of about 0.8 microns.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 schematically illustrates a semiconductor substrate with a first SiO.sub.2 and a first Si.sub.3N.sub.4 layer already formed on the top surface.

(2) FIG. 2 schematically illustrates the patterning of the first SiO.sub.2 and the first Si.sub.3N.sub.4 layer to define a trench etching mask.

(3) FIG. 3 schematically illustrates the forming of a trench into the substrate by a first etching process, using the first SiO.sub.2 and the first Si.sub.3N.sub.4 layer as the etching mask.

(4) FIG. 4 schematically illustrates the trench structure after the deposition of the second SiO.sub.2 and the second Si.sub.3N.sub.4 layer on the substrate.

(5) FIG. 5 schematically illustrates the trench structure after the removal of the second Si.sub.3N.sub.4 and the second SiO.sub.2 layer except on the trench sidewall.

(6) FIG. 6 schematically illustrates the result of the thermal oxidation process to grow oxide in the trench bottom and trench top corner.

(7) FIG. 7 schematically illustrates the substrate after removing all Si.sub.3N.sub.4 and SiO.sub.2 layer. The trench is clearly shown with increased radius of curvature at both trench bottom and at trench top corner.

DETAILED DESCRIPTION

(8) Referring to FIGS. 1 through 7, wherein like reference numerals refer to like components in the various views.

(9) Some embodiments of the present invention will be described hereafter with reference to the drawings. Drawings FIG. 1-7 are schematic cross-sectional elevation views of a semi-conductor substrate to illustrate the sequence of process steps in forming trenches inside the substrate. No intent is made to illustrate specific size or proportions, as these will be well understood by those skilled in the art of such semi-conductor devices with the aid of the following descriptions.

(10) The method comprises the following steps.

(11) With reference to FIG. 1, there is provided with a semiconductor substrate 1 and the first step is to form a first SiO.sub.2 layer 2 on the top surface of substrate 1, and then the first Si.sub.3N.sub.4 layer 3 on the top of the first SiO.sub.2 layer 2. The first SiO.sub.2 layer 2 can be formed either by a thermal oxidation process or by a CVD (chemical vapor deposition) process. The first Si.sub.3N.sub.4 layer 3 can be formed by a CVD process. The layers should be deposited with a process that produces an isotropic or conformal coating, and may also be deposited by an ALD process (Atomic Layer Deposition).

(12) Then in the next step, lithography and etching process is performed to pattern the first SiO.sub.2 layer 2 and the first Si.sub.3N.sub.4 layer 3, with the result shown in FIG. 2.

(13) The next step is to etch trench 101 into the substrate 1, with the result shown in FIG. 3. This trench etching step uses the first SiO.sub.2 layer 2 and the first Si.sub.3N.sub.4 layer 3 as an etching mask. The resulting trench 101 has top corners 11, having a sharp, almost square shape. The trench 101 has a width of 2r.sub.1. The trench bottom 21 has a radius of curvature of about r.sub.1.

(14) After the trench is etched, in a subsequent step, a second SiO.sub.2 layer 4 and a second Si.sub.3N.sub.4 layer 5 are formed conformal to the substrate, with the result of this step illustrated by FIG. 4. The second SiO.sub.2 layer 4 and the second Si.sub.3N.sub.4 layer 5 can be formed by CVD or ALD process.

(15) Then, in a subsequent step, anisotropic etching is done to sequentially to remove the second Si.sub.3N.sub.4 layer 5 and the second SiO.sub.2 layer 4 except on the trench sidewall, with the result of this step shown in FIG. 5. Such anisotropic etching is readily conducted in commercial semi-conductor processing equipment, such as a LAM 4300 etching apparatus as a non-limiting example, and preferably under dry etching conditions with thriflouromethane (CHF.sub.3) gas.

(16) The next step is a thermal oxidation process. Thermal oxidation of silicon preferably occurs at about 1,050 C. using water vapor as the oxidizer, rather than dry oxygen. The Si.sub.3N.sub.4 layers 3 and 5 are impermeable to the oxidizing agents, while the oxidizing agents can penetrate the SiO.sub.2 layer 2 and 4. The Si substrate at the bottom of the trench is no longer protected by second pair of Si.sub.3N.sub.4 and SiO.sub.2 layers (Si.sub.3N.sub.4 layer 5 and SiO.sub.2 layer 4). However, the removal of the planar portions of the Si.sub.3N.sub.4 layer 5 and SiO.sub.2 layer 4 at the top of the substrate leaves a very thin SiO.sub.2 edge at the top corners of the trench which very short oxygen diffusion path. Therefore, the thermal oxide 6 grows fastest in the trench bottom and slightly slower in trench top corners, as shown in FIG. 6, where the oxygen more readily diffuses through the thin SiO2 layer 4 that was not consumed in the anisotropic etching. The slower diffusion of oxidizing agent in the SiO.sub.2 layer 4 down the sidewalls under the Si.sub.3N.sub.4 layer 5 more slowly expands the SiO.sub.2 thickness in the sidewalls as Si is consumed. As this thermal oxidation process consumes the Si or other semiconductor material in the trench bottom and at trench top corner faster than in the sidewalls, it also changes the shape of the trench, rounding otherwise sharp corners and increasing the curvature of the bottom. The size increase of the bottom radius from r.sub.1 to r.sub.2 is readily controlled by oxidation time under these conditions. As the Si at the trench corner is consumed by growing SiO2 the approximately 2.4:1 thermal expansion causes the upper planar Si.sub.3N.sub.4 layer 5 at the trench corner to lift away from Si.sub.3N.sub.4 layer 5 on the sidewalls. Simulations of trench formation and etching processes disclosed herein indicate a 40 minute thermal oxidation time for this step expands the trench radius from 0.4 m to 0.6 m, resulting in a trench with a width of 0.8 m (2r.sub.1) and a depth of about 5 m. Conditions for other trench sizes, aspect ratios and local curvature can readily be determined by such simulations by varying initial sizes and etch times.

(17) In the next step, all Si.sub.3N.sub.4 layers and SiO.sub.2 layers are stripped by wet etching or CDE (chemical dry etching) process, to provide the result shown in FIG. 7. It can be clearly seen that, the trench 102 has different shape than trench 101. The trench top 12 is rounded. The width of trench 102 is still 2r.sub.1. The trench bottom 22 has a radius of curvature larger than r.sub.1. Therefore, both the radius of curvature at trench bottom and at trench top corner is increased. The trench depth can be readily increased beyond 5 m by increasing the initial etch depth through the mask opening formed in the initial Si.sub.3N.sub.4 layer 3 and the first SiO.sub.2 layer 2.

(18) Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. For example, semiconductor substrate material provided in this invention can be selected from the group of materials that consist of silicon and silicon carbide. While the invention has been described in connection with a preferred embodiment, it is not intended to limit the scope of the invention to the particular form set forth, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents as may be within the spirit and scope of the invention as defined by the appended claims.