A semiconductor device includes: a semiconductor body having a first surface, a second surface opposite to the first surface in a vertical direction, an active region, and a sensor region arranged adjacent to the active region in a horizontal direction; transistor cells at least partly integrated in the active region, each transistor cell including a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region; at least one sensor cell at least partly integrated in the sensor region, each sensor cell including a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region; and an intermediate region arranged between the active region and the sensor region, the intermediate region including a drift region and an undoped semiconductor region extending from the first surface into the drift region.

A semiconductor device includes: a semiconductor body having a first surface, a second surface opposite to the first surface in a vertical direction, an active region, and a sensor region arranged adjacent to the active region in a horizontal direction; transistor cells at least partly integrated in the active region, each transistor cell including a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region; at least one sensor cell at least partly integrated in the sensor region, each sensor cell including a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region; and an intermediate region arranged between the active region and the sensor region, the intermediate region including a drift region and an undoped semiconductor region extending from the first surface into the drift region.

A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

An active region has first and second cell regions respectively disposed in a main IGBT and a sensing IGBT. The second cell region has a detecting region in which the sensing IGBT is disposed and an extracting region that surrounds a periphery of the detecting region. A resistance region containing polysilicon and connected to the sensing IGBT is provided on the semiconductor substrate, in the extracting region. The resistance region connected to the sensing IGBT has a first portion connected to the gate electrodes of the sensing IGBT and a second portion connecting the first portion to the gate runner, and configures a built-in resistance of the second portion having a resistance value in a range from 10Ω to 5000Ω. As a result, a trade-off relationship between enhancing ESD tolerance of a current sensing region that includes the sensing IGBT and reducing transient sensing voltage may be improved.

A semiconductor device includes a semiconductor layer with an inner portion, an outer portion laterally surrounding the inner portion, and a transition portion laterally surrounding the inner portion and separating the inner portion and the outer portion. A first electric element includes a first doped region formed in the inner portion and a second doped region formed in the outer portion. The first electric element is configured to at least temporarily block a voltage applied between the first doped region and the second doped region. A trench isolation structure extends from a first surface into the semiconductor layer and segments at least one of the inner portion, the transition portion, and the outer portion.

A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed along an outer peripheral region of the semiconductor substrate. The equipotential ring electrode is connected to the channel stopper through the first contact hole, and is connected to the first field plate, and is connected to the second field plate through a second contact hole formed in the insulating film.

A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed along an outer peripheral region of the semiconductor substrate. The equipotential ring electrode is connected to the channel stopper through the first contact hole, and is connected to the first field plate, and is connected to the second field plate through a second contact hole formed in the insulating film.

The invention achieves a lower noise of a sense signal of a FET-type hydrogen sensor. For solving the above problem, one aspect of a sensor system of the invention includes a reference device and a sensor device configured using FETs on a substrate, and further, well potentials of the reference device and the sensor device are electrically isolated from each other.

A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure includes a first doping region at a front side surface of the substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the substrate to at least a part of the front side surface in contact with the wiring structure. An edge termination doping region laterally surrounds the first and second active areas. The edge termination doping region and the first doping region have a first conductivity type, and the common doping region has a second conductivity type. A resistive connection between the edge termination doping region and the first doping region is present at least during reverse operating conditions of the semiconductor device.

A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.