Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.

An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and electrically connected to the first conductive feature. The second conductive feature includes a dual damascene structure and further includes a top portion within both a line portion and a via portion of the second conductive feature and a bottom portion in the via portion of the second conductive feature. The bottom portion comprises a different conductive material than the top portion, and a thickness of the bottom portion is at least about twenty percent of a total thickness of the via portion of the second conductive feature.

A MOS capacitor, a method of fabricating the same, and a semiconductor device using the same are provided. The MOS capacitor is arranged in an outermost cell block of the semiconductor device employing an open bit line structure. The MOS capacitor includes a first electrode arranged in a semiconductor substrate, a dielectric layer arranged on a semiconductor substrate, and a second electrode arranged on the dielectric layer and including a dummy bit line.

A method of manufacturing a semiconductor device, including: providing a substrate including a first cell and a second cell that are arranged in a first direction; forming a plurality of first metal strips extending in the first direction and arranged in a second direction on a first plane; forming a first trench over a boundary between the first cell and the second cell, wherein a bottom surface of the first trench is on a second plane over the first plane; filling the first trench with a non-conductive material, resulting in a separating wall which extends in the first direction; and forming a plurality of second metal strips extending in the second direction on a third plane over the second plane, wherein a first second metal strip and a second second metal strip separated from each other by the separating wall; wherein the second direction is orthogonal to the first direction.

Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

A display apparatus includes laminated glass comprising an interlayer film laminated between a pair of glass plates; and an irradiation device irradiating the laminated glass with light rays, wherein the interlayer film comprises a thermoplastic resin and a luminescent material, wherein an output of the light rays radiated from the irradiation device is equal to or less than 1 mW, and wherein the laminated glass emits light at a luminance of equal to or greater than 1 cd/m.sup.2 when being irradiated with the light rays.

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

An RF SOI switch includes patterned or self-aligned low-k features (i.e., low-k polymer structures or voids) in the PMD and/or subsequently formed inter-metal dielectric layers to reduce capacitive coupling. All portions of the dielectric layers through which metal contact/via structures pass are pre-designated as reserved regions, and formation of the low-k features is restricted to interstitial regions located between adjacent reserved regions. After the low-k features are formed, dielectric material is deposited into all reserved regions, and then the metal contact/via structures are formed according to standard practices through the dielectric material disposed in the reserved regions. The low-k features are formed by polymer material sandwiched between two passivation layers. Optional openings are formed through the upper passivation layer, and then the polymer material is asked out to generate void-type features. Optionally, polymer is spin-coated over the metal line structures, then etched back to form self-aligned low-k features.

A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening.

A method for manufacturing a semiconductor structure is provided. The method for manufacturing a semiconductor structure includes forming an organosilicon layer over a substrate and etching the organosilicon layer to have a trench. The method for manufacturing a semiconductor structure further includes forming a conductive structure in the trench. In addition, the organosilicon layer is made of a material including Si—C bonding and Si—O bonding, and a ratio of an amount of the Si—C bonding to an amount of the Si—O bonding is greater than about 0.2.