Embodiments regard micro-size devices formed by etch of sacrificial epitaxial layers. An embodiment of a method includes forming a plurality of epitaxial layers on a sapphire crystal, wherein the epitaxial layers include a buffer layer on the sapphire crystal, a sacrificial layer above the buffer layer, and one or more device layers above the sacrificial layer; etching to singulate the semiconductor devices, the etching being through the one or more device layers and wholly or partially through the sacrificial layer; electrochemical etching of the sacrificial layer; and lift-off of one or more semiconductor devices from the buffer layer.

A method of producing microelectronic components includes forming a functional layer system; applying a laminar carrier to the functional layer system; attaching a workpiece to a workpiece carrier; utilizing incident radiation of a laser beam is focused in a boundary region between a growth substrate and the functional layer system, and a bond between the growth substrate and the functional layer system in the boundary region is weakened or destroyed; separating a functional layer stack from the growth substrate, wherein a vacuum gripper having a sealing zone that circumferentially encloses an inner region is applied to the reverse side of the growth substrate, a negative pressure is generated in the inner region such that separation of the functional layer stack from the growth substrate is initiated in the inner region; and the growth substrate held on the vacuum gripper is removed from the functional layer stack.

A method of fabricating a micro light emitting diode (micro LED) apparatus includes forming a first substrate including a first silicon layer, a second silicon layer, and a silicon oxide layer sandwiched between the first silicon layer and the second silicon layer; forming a plurality of micro LEDs on a side of the second silicon layer distal to the silicon oxide layer; bonding the first substrate having the plurality of micro LEDs with a second substrate; and removing the silicon oxide layer and the first silicon layer.

A method for manufacturing an electronic device includes the following: forming an island-shaped peeling layer onto a substrate; stacking a resin layer all over the peeling layer; forming a barrier layer over the resin layer; forming an electronic-circuit layer onto the upper surface of the barrier layer; and peeling off the resin layer from the substrate and the peeling layer.

The present invention discloses a super-flexible transparent semiconductor film and a preparation method thereof, the method includes: providing an epitaxial substrate; growing a sacrificial layer on the epitaxial substrate; stacking and growing at least one layer of Al.sub.1-nGa.sub.nN epitaxial layer on the sacrificial layer, wherein 0<n≤1; growing a nanopillar array containing GaN materials on the Al.sub.1-nGa.sub.nN epitaxial layer; etching the sacrificial layer so as to peel off an epitaxial structure on the sacrificial layer as a whole; and transferring the epitaxial structure after peeling onto a surface of the flexible transparent substrate. Compared to traditional planar films, the present invention can not only improve the crystal quality by releasing stress, but also improve flexibility and transparency through characteristics of the nanopillar materials. In addition, a total thickness of the buffer layer and the sacrificial layer required by the epitaxial structure can be small, and there is no need for additional catalyst during an epitaxial growth process, which is beneficial for reducing epitaxial costs and process difficulty. The present invention is practical in use, and can provide technical support for invisible semiconductor devices and super-flexible devices.

A stacked structure includes: an insulating substrate; a graphene film that is formed on the insulating substrate; and a protective film that is formed on the graphene film and is made of a transition metal oxide, which is, for example, Cr.sub.2O.sub.3. Thereby, at the time of transfer of the graphene, polymeric materials such as a resist are prevented from directly coming into contact with the graphene and nonessential carrier doping on the graphene caused by a polymeric residue of the resist is suppressed.

A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.

Described herein are systems and methods of utilizing nanochannels generated in the sacrificial layer of a semiconductor substrate to increase epitaxial lift-off speeds and facilitate reusability of GaAs substrates. The provided systems and methods may utilize unique nanochannel geometries to increase the surface area exposed to the etchant and further decrease etch times.

An apparatus includes a base including a receiving portion that receives a substrate on which semiconductor elements are disposed; and at least one ultrasonic generator that generates and applies ultrasonic waves to the substrate placed in the base.

A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.