The application relates to a substrate structure, an on-chip structure, and a method for manufacturing the on-chip structure. The substrate structure includes a substrate body and an electrothermal layer. The electrothermal layer is arranged on a surface of the substrate body for growing an epitaxial layer. In an actual lift off process of the epitaxial layer, only the electrothermal layer is electrically conducted to an external power supply via an electrode, and heating of the electrothermal layer is utilized to heat the epitaxial layer, therefore, a part of the epitaxial layer in contact with the substrate structure can be thermally decomposed and separated from the substrate structure.

A method for making a field effect transistor includes providing a graphene nanoribbon composite structure. The graphene nanoribbon composite structure includes a substrate and a plurality of graphene nanoribbons spaced apart from each other. The plurality of graphene nanoribbons are located on the substrate and extend substantially along a same direction, and each of the plurality of graphene nanoribbons includes a first end and a second end opposite to the first end. A source electrode is formed on the first end, and a drain electrode is formed on the second end. The source electrode and the drain electrode are electrically connected to the plurality of graphene nanoribbons. An insulating layer is formed on the plurality of graphene nanoribbons, and the plurality of graphene nanoribbons are between the insulating layer and the substrate. A gate is formed on a surface of the insulating layer away from the substrate.

The present disclosure relates to a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer. In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.

A method for manufacturing a semiconductor substrate according to the present invention includes preparing a seed substrate containing a semiconductor material, forming an ion implanted layer at a certain depth from a front surface of a main surface of the seed substrate by implanting ions into the seed substrate, growing a semiconductor layer on the main surface of the seed substrate with a vapor-phase synthesis method, and separating a semiconductor substrate including the semiconductor layer and a part of the seed substrate by irradiating the front surface of the main surface of at least any of the semiconductor layer and the seed substrate with light.

A method is provided for fabricating a thin-film semiconductor substrate by forming a porous semiconductor layer conformally on a reusable semiconductor template and then forming a thin-film semiconductor substrate conformally on the porous semiconductor layer. An inner trench having a depth less than the thickness of the thin-film semiconductor substrate is formed on the thin-film semiconductor substrate. An outer trench providing access to the porous semiconductor layer is formed on the thin-film semiconductor substrate and is positioned between the inner trench and the edge of the thin-film semiconductor substrate. The thin-film semiconductor substrate is then released from the reusable semiconductor template.

A method to fill the flowable material into the semiconductor assembly module gap regions is described. In an embodiment, multiple semiconductor units are formed on the substrate to create an array module; the array module is attached to a backplane having circuitry to form the semiconductor assembly module in which multiple gap regions are formed inside the semiconductor assembly module and edge gap regions are formed surround an edge of the assembly module; The flowable material is forced inside the gap regions by performing the high acting pressure environment and then cured to be a stable solid to form a robustness structure. A semiconductor convert module is formed by removing the substrate utilizing a substrate removal process. A semiconductor driving module is formed by utilizing a connecting layer on the semiconductor convert module. In one embodiment, a vertical light emitting diode semiconductor driving module is formed to light up the vertical LED array. In another one embodiment, multiple color emissive light emitting diodes semiconductor driving module is formed to display color images. In another embodiment, multiple patterns of semiconductor units having multiple functions semiconductor driving module is formed to provide multiple functions for desire application.

A manufacturing method for a semiconductor element includes providing a mask including an opening on a surface of a substrate while leaving a step difference in the mask at an upper surface region around the opening, epitaxially growing a semiconductor from the surface exposed through the opening to over the upper surface region around the opening, to produce a semiconductor element including a semiconductor layer including a first surface to which the step difference is transferred, and dry-etching the first surface of the semiconductor layer to transfer the step difference, the first surface being a contact surface with the mask before the dry etching is performed. The mask contains an element that serves as a donor or an acceptor in the semiconductor layer.

A method of manufacturing a semiconductor device includes irradiation of laser on a semiconductor substrate and cutting of the semiconductor substrate. The laser is irradiated on the semiconductor substrate while moving a focal point of the laser inside the semiconductor substrate. The semiconductor includes a specific crystal plane that is easier to be cleaved, and that is tilted to the surface of the semiconductor substrate. The irradiation of the laser includes repetition of a specific modified layer formation process in which one of the specific modified layers along the specific crystal plane is formed by moving the focal point along the specific crystal plane. In the irradiation of the laser, the specific modified layers are arranged in a direction parallel to the surface of the semiconductor substrate. In the cutting of the semiconductor substrate, the semiconductor substrate is cut along the specific modified layers.

A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least a portion of the array of memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

A method of fabricating the vertical field effect transistor includes forming a dielectric layer on a metal semiconductor alloy layer that is present on a substrate of a semiconductor material. The dielectric layer is bonded to a supporting substrate. The substrate of the semiconductor material is cleaved, wherein a remaining portion of the semiconductor material provides a semiconductor surface layer in direct contact with the metal semiconductor alloy layer. A vertical fin type field effect transistor (FinFET) is formed atop the stack of the semiconductor surface layer, the metal semiconductor alloy layer, the dielectric layer and the supporting substrate, wherein the semiconductor surface layer provides at least one of a source region or a drain region of the FinFET and the metal semiconductor alloy provides a contact to the source region or the drain region of the FinFET.