A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.

A semiconductor device and method for fabricating a semiconductor device, comprising a paste layer is disclosed. In one example the method comprises attaching a substrate to a carrier, wherein the substrate comprises a plurality of semiconductor dies. A layer of a paste is applied to the substrate. The layer above cutting regions of the substrate is structured. The substrate is cut along the cutting regions.

A method of manufacturing a semiconductor device includes forming a light blocking film configured to block first light within a first wavelength band on an edge region of an upper surface of a light-transmitting carrier substrate; forming a photosensitive adhesive layer on the upper surface of the light-transmitting carrier substrate to at least partially cover the light blocking film; bonding a product substrate to the upper surface of the light-transmitting carrier substrate using the photosensitive adhesive layer; partially curing the photosensitive adhesive layer by irradiating the light through the light-transmitting carrier substrate, wherein a portion of the photosensitive adhesive layer overlapping the light blocking film is not cured; processing the product substrate to form a plurality of semiconductor devices after the partially curing of the photosensitive adhesive layer; and cutting the product substrate such that the plurality of semiconductor devices are cut into a plurality of separate individual semiconductor devices.

A method of manufacturing a semiconductor device includes forming a light blocking film configured to block first light within a first wavelength band on an edge region of an upper surface of a light-transmitting carrier substrate; forming a photosensitive adhesive layer on the upper surface of the light-transmitting carrier substrate to at least partially cover the light blocking film; bonding a product substrate to the upper surface of the light-transmitting carrier substrate using the photosensitive adhesive layer; partially curing the photosensitive adhesive layer by irradiating the light through the light-transmitting carrier substrate, wherein a portion of the photosensitive adhesive layer overlapping the light blocking film is not cured; processing the product substrate to form a plurality of semiconductor devices after the partially curing of the photosensitive adhesive layer; and cutting the product substrate such that the plurality of semiconductor devices are cut into a plurality of separate individual semiconductor devices.

A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs are in the semiconductor device. Each of the TSVs has a first surface and a second surface opposite to the first surface. The first seal ring is located in proximity to an edge of the semiconductor structure and is physically connected to the first surface of each of the TSVs. The second seal ring is physically connected to the second surface of each of the TSVs.

A manufacturing method of chips includes forming modified layers that become points of origin of dividing along planned dividing lines, grinding the back surface of the wafer by grinding abrasive stones to thin the wafer into a finished thickness, and dividing the wafer into the chips along the planned dividing lines using the modified layers as the points of origin. The manufacturing method also includes sticking an expanding tape having elasticity to the back surface of the wafer for which grinding processing has been executed, expanding the expanding tape and widening the interval between the respective chips along the planned dividing lines.

A manufacturing method of chips includes forming modified layers that become points of origin of dividing along planned dividing lines, grinding the back surface of the wafer by grinding abrasive stones to thin the wafer into a finished thickness, and dividing the wafer into the chips along the planned dividing lines using the modified layers as the points of origin. The manufacturing method also includes sticking an expanding tape having elasticity to the back surface of the wafer for which grinding processing has been executed, expanding the expanding tape and widening the interval between the respective chips along the planned dividing lines.

An integrated circuit apparatus includes a silicon-on-insulator (SOI) substrate comprising a silicon layer overlying an insulator layer; a first silicon fin region formed in a first region of the silicon layer, the first silicon fin region comprising a first source region, a first drain region, and a first channel region; a second silicon fin region formed in a second region of the silicon layer, the second silicon fin region comprising a second source region, a second drain region, and a second channel region; a gate dielectric layer formed on the first, second, and third surface regions of the first silicon fin region, and on the third and fourth surface regions of the second silicon fin region; a dual-gate FinFET, comprising the second drain, source and channel regions in the second silicon fin region; and a tri-gate FinFET, comprising the first drain, source and channel regions.