A hermetically sealed electronic package may include a thermal panel having a panel interior surface and a panel exterior surface with electronic device(s) in thermal communication with the panel interior surface. An enclosure, isolating environmental communication from internal electronic devices and modules, may be coupled to the thermal panel, and the enclosure may have an enclosure interior surface and an enclosure exterior surface. A plurality of electrical feedthroughs may be coupled to the package enclosure for signal and data transmission, and the conducting pin(s) in every electrical feedthrough may be bonded by a hydrophobic sealing material for harsh environmental electrical signal, data and power transmission. The ratio of sealing length over sealing bead diameter in the electrical feedthrough subassembly may have a preferred value from 2 to 3; and the ratio of the sealing bead diameter over pin diameter in the electrical feedthrough subassembly may have a preferred value from 1.5 to 2.0, where a preferred thermal stress resistance could be designed for making highly hermetic sealed electronic package.

A hermetically sealed electronic package may include a thermal panel having a panel interior surface and a panel exterior surface with electronic device(s) in thermal communication with the panel interior surface. An enclosure, isolating environmental communication from internal electronic devices and modules, may be coupled to the thermal panel, and the enclosure may have an enclosure interior surface and an enclosure exterior surface. A plurality of electrical feedthroughs may be coupled to the package enclosure for signal and data transmission, and the conducting pin(s) in every electrical feedthrough may be bonded by a hydrophobic sealing material for harsh environmental electrical signal, data and power transmission. The ratio of sealing length over sealing bead diameter in the electrical feedthrough subassembly may have a preferred value from 2 to 3; and the ratio of the sealing bead diameter over pin diameter in the electrical feedthrough subassembly may have a preferred value from 1.5 to 2.0, where a preferred thermal stress resistance could be designed for making highly hermetic sealed electronic package.

A laser element includes a light emitting portion that has at least two or more light emitting points, and a terminal member on which the light emitting portion is mounted. The terminal member includes a base portion that has a mounting surface on which the light emitting portion is mounted, a base that has a front surface where the base portion is provided substantially at a center, and four pins that extend from a rear surface of the base. The light emitting portion is positioned in a range surrounded by the four pins as viewed from the front surface of the base.

According to the present invention, a semiconductor device includes a substrate having a metallic pattern formed on a top surface of the substrate, a semiconductor chip provided on the metallic pattern, a back surface electrode terminal in flat plate form connected to the metallic pattern with a wire, a front surface electrode terminal in flat plate form, the front surface electrode terminal being in parallel to the back surface electrode terminal above the back surface electrode terminal, extending immediately above the semiconductor chip, and being directly joined to a top surface of the semiconductor chip, a case surrounding the substrate and a seal material for sealing an inside of the case.

According to the present invention, a semiconductor device includes a substrate having a metallic pattern formed on a top surface of the substrate, a semiconductor chip provided on the metallic pattern, a back surface electrode terminal in flat plate form connected to the metallic pattern with a wire, a front surface electrode terminal in flat plate form, the front surface electrode terminal being in parallel to the back surface electrode terminal above the back surface electrode terminal, extending immediately above the semiconductor chip, and being directly joined to a top surface of the semiconductor chip, a case surrounding the substrate and a seal material for sealing an inside of the case.

A packaged power transistor device includes a Direct-Bonded Copper (DBC) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

A hermetically sealed electronic package may include a thermal panel having a panel interior surface and a panel exterior surface with electronic device(s) in thermal communication with the panel interior surface. An enclosure, isolating environmental communication from internal electronic devices and modules, may be coupled to the thermal panel, and the enclosure may have an enclosure interior surface and an enclosure exterior surface. A plurality of electrical feedthroughs may be coupled to the package enclosure for signal and data transmission, and the conducting pin(s) in every electrical feedthrough may be bonded by a hydrophobic sealing material for harsh environmental electrical signal, data and power transmission. The ratio of sealing length over sealing bead diameter in the electrical feedthrough subassembly may have a preferred value from 2 to 3; and the ratio of the sealing bead diameter over pin diameter in the electrical feedthrough subassembly may have a preferred value from 1.5 to 2.0, where a preferred thermal stress resistance could be designed for making highly hermetic sealed electronic package.

A hermetically sealed electronic package may include a thermal panel having a panel interior surface and a panel exterior surface with electronic device(s) in thermal communication with the panel interior surface. An enclosure, isolating environmental communication from internal electronic devices and modules, may be coupled to the thermal panel, and the enclosure may have an enclosure interior surface and an enclosure exterior surface. A plurality of electrical feedthroughs may be coupled to the package enclosure for signal and data transmission, and the conducting pin(s) in every electrical feedthrough may be bonded by a hydrophobic sealing material for harsh environmental electrical signal, data and power transmission. The ratio of sealing length over sealing bead diameter in the electrical feedthrough subassembly may have a preferred value from 2 to 3; and the ratio of the sealing bead diameter over pin diameter in the electrical feedthrough subassembly may have a preferred value from 1.5 to 2.0, where a preferred thermal stress resistance could be designed for making highly hermetic sealed electronic package.

A packaged power transistor device includes a Direct-Bonded Copper (DBC) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

A stem for a semiconductor package, includes an eyelet having a first surface, a second surface opposite to the first surface, and a through-hole penetrating the eyelet from the first surface to the second surface, a metal base bonded to the second surface of the eyelet so as to cover one end of the through-hole, and a metal block having one end thereof inserted into the through-hole and bonded to the metal base inside the through-hole, and another end projecting from the first surface of the eyelet and including a device mounting surface on which a semiconductor device is mounted. The metal base has a thermal conductivity higher than or equal to a thermal conductivity of the eyelet, and a surface at the one end of the metal block matches the second surface of the eyelet.