A multi-wavelength integrated device (5) including plural semiconductor lasers (6) and plural modulators (7) modulating output beams of the plural semiconductor lasers (6) respectively is mounted on the stem (1). Plural leads (10) penetrates through the stem (1) and are connected to the plural semiconductor lasers (6) and the plural modulators (7) respectively. Each lead (10) is a coaxial line in which plural layers are concentrically overlapped with one another. The coaxial line includes a high frequency signal line (12) transmitting a high frequency signal to the modulator (7), a GNU line (14), and a feed line (16) feeding a DC current to the semiconductor laser (6). The high frequency signal line (12) is arranged at a center of the coaxial line. The GND line (14) and the feed line (16) are arranged outside the high frequency signal line (12).

A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.

A package encloses a power semiconductor die and has a package body with a package top side, package footprint side and package sidewalls. The die has first and second load terminals for blocking a blocking voltage. A lead frame structure electrically and mechanically couples the package to a support and includes an outside terminal extending out of the package footprint side and/or the sidewalls, and is electrically connected with the first load terminal. A top layer arranged at the package top side is electrically connected with the second load terminal. A creepage length between the electrical potential of the outside terminal and the electrical potential of the top layer is defined by a package body surface contour. The surface contour is formed at least by the package top side and package sidewall. At least one structural feature also forms the surface contour is configured to increase the creepage length.

A semiconductor device includes a semiconductor chip, a substrate having a main surface on which the semiconductor chip is arranged, a resin case which has a storage space therein and a side wall, the side wall having an injection path extending from the storage space to a device exterior, the resin case having a first opening at a bottom side thereof, connecting the storage space to the device exterior, the substrate being disposed on the resin case, at a main surface side of the substrate facing at the bottom side of the resin case, and a sealing material filling the storage space and the injection path.

An electronic component mounting package includes a dielectric substrate between first portions of a pair of signal terminals that protrude from one side in a thickness direction from a first face of a base body. This dielectric substrate has a height lower than a height of the first portions. When an electronic component is mounted, a bonding wire is connected to a tip of each of the first portions to electrically connect the first portion to the electronic component.

A first portion of an element-side terminal of a semiconductor element includes a projection. A second portion of the case-side terminal of a case includes a recess which comes into contact with a projection. The projection includes a first end surface and a second end surface continuous with the top surface. The recess includes a first lateral surface which is in continuous with a bottom surface and is in contact with the first end surface, and a second lateral surface which is in contact with the bottom surface and is in contact with the second end surface. As viewed from a lateral wall side, the first end surface and the first lateral surface are inclined in a first direction, and the second end surface and the second lateral surface are inclined in a second direction intersecting the first direction.

A transistor outline package is provided that includes a header having an upper surface, a lower surface, an inner surface, and a mounting area for an optoelectronic component in the inner surface. The header has a signal pin configured to connect an optoelectronic component. The signal pin is disposed in a feedthrough and protrudes from the lower surface. A printed circuit board attached on the signal pin substantially coaxially thereto. The printed circuit board is mechanically and electrically connected to the header by a metal block arranged adjacent to the feedthrough to provide grounding.

A transistor outline package is provided that includes a header with a mounting area for an optoelectronic component. The header has a signal pin disposed in a feedthrough. The feedthrough is filled with an insulating material made of glass and/or glass ceramic. The feedthrough has a recessed area on at least one side that is not completely filled up with the insulating material. The recessed area defines a cavity at least partially around the signal pin and the signal pin has an enlarged portion in the recessed area.

The present invention relates to a new electronic component package and its manufacturing method, especially the package of an optoelectronic component. The package comprises an electronically conductive base, an electronically conductive cap, and at least one electronic component. The base has an upper surface, a lower surface, and at least one through hole sealed with a conducting feedthrough surrounded by a ring of insulating material. The electronic component is fixed on the upper surface of the base and is electrically connected to the conducting feedthroughs and/or the base. The base and the cap are sealed by welding.

A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.