A first wiring member bends at a first bent portion in the shape of the letter “L” in a side view and includes a first horizontal portion parallel to the principal surface of a semiconductor chip and a first vertical portion perpendicular to the first horizontal portion. A second wiring member bends at a second bent portion in a direction opposite to the first wiring member in the shape of the letter “L” in the side view and includes a second horizontal portion flush with the first horizontal portion and a second vertical portion a determined distance distant from the first vertical portion and parallel to the first vertical portion. A wiring holding portion fills a gap between the first and second vertical portions and a gap between the first and second bent portions. Therefore, stress applied to the vicinity of the first or second bent portion is relaxed.

A first wiring member bends at a first bent portion in the shape of the letter “L” in a side view and includes a first horizontal portion parallel to the principal surface of a semiconductor chip and a first vertical portion perpendicular to the first horizontal portion. A second wiring member bends at a second bent portion in a direction opposite to the first wiring member in the shape of the letter “L” in the side view and includes a second horizontal portion flush with the first horizontal portion and a second vertical portion a determined distance distant from the first vertical portion and parallel to the first vertical portion. A wiring holding portion fills a gap between the first and second vertical portions and a gap between the first and second bent portions. Therefore, stress applied to the vicinity of the first or second bent portion is relaxed.

A semiconductor device in which a semiconductor element mounted on a laminate substrate and an electrically conductive connection member are sealed with a sealing material, includes: a primer layer in an interface between the sealing material and sealed members including the laminate substrate, the semiconductor element, and the electrically conductive connection member, in which the sealing material includes a first sealing layer which is provided in contact with the primer layer; and a second sealing layer which covers the first sealing layer, the semiconductor device satisfies α.sub.p≥α.sub.1>α.sub.2 in which α.sub.p, α.sub.1, and α.sub.2 represent coefficients of linear thermal expansion of the primer layer, the first sealing layer, and the second sealing layer, respectively, α.sub.c≥15×10.sup.−6/° C. in which α.sub.c represents a composite coefficient of linear thermal expansion of the sealing layers, and E.sub.c≥5 GPa or more in which E.sub.c represents a composite Young's modulus of the sealing layers.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

A method is provided for producing a hermetically sealed housing having a semiconductor component. The method comprises introducing a housing having a housing body and a housing cover into a process chamber. The housing cover closes off a cavity of the housing body and is attached in a gas-tight manner to the housing body. At least one opening is formed in the housing. At least one semiconductor component is arranged in the cavity. The method furthermore comprises generating a vacuum in the cavity by evacuating the process chamber, and also generating a predetermined gas atmosphere in the cavity and the process chamber. The method moreover comprises applying sealing material to the at least one opening while the predetermined gas atmosphere prevails in the process chamber.

A method is provided for producing a hermetically sealed housing having a semiconductor component. The method comprises introducing a housing having a housing body and a housing cover into a process chamber. The housing cover closes off a cavity of the housing body and is attached in a gas-tight manner to the housing body. At least one opening is formed in the housing. At least one semiconductor component is arranged in the cavity. The method furthermore comprises generating a vacuum in the cavity by evacuating the process chamber, and also generating a predetermined gas atmosphere in the cavity and the process chamber. The method moreover comprises applying sealing material to the at least one opening while the predetermined gas atmosphere prevails in the process chamber.

A semiconductor device of embodiments includes an insulating substrate, a first main terminal, a second main terminal, an output terminal, a first metal layer connected to the first main terminal, a second metal layer connected to the second main terminal, a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal, a first semiconductor chip and a second semiconductor chip provided on the first metal layer, a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer, and a conductive member on the second metal layer. Then, the second metal layer includes a slit. The conductive member is provided between the end portion of the second metal layer and the slit.

A semiconductor device of embodiments includes an insulating substrate, a first main terminal, a second main terminal, an output terminal, a first metal layer connected to the first main terminal, a second metal layer connected to the second main terminal, a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal, a first semiconductor chip and a second semiconductor chip provided on the first metal layer, a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer, and a conductive member on the second metal layer. Then, the second metal layer includes a slit. The conductive member is provided between the end portion of the second metal layer and the slit.

A semiconductor device includes: an insulating substrate; a first semiconductor element connected to the insulating substrate; a conductive member disposed on the insulating substrate, and including a first opposing portion and a second opposing portion located opposite each other with respect to the first semiconductor element in plan view; a first wire connected to the first semiconductor element and the first opposing portion; and a second wire connected to the first semiconductor element and the second opposing portion, and located opposite the first wire with respect to a connection point where the first wire and the first semiconductor element are connected to each other in plan view.