In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.

In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.

A semiconductor module arrangement includes a housing, a first semiconductor substrate arranged inside the housing, a second semiconductor substrate arranged inside the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses. Further during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses. At least a first sub-group of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and at least a first sub-group of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.

A semiconductor module arrangement includes a housing, a first semiconductor substrate arranged inside the housing, a second semiconductor substrate arranged inside the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses. Further during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses. At least a first sub-group of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and at least a first sub-group of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.

A power semiconductor module includes an insulating substrate, a first conductive circuit pattern, a second conductive circuit pattern, a first semiconductor device, a second semiconductor device, a sealing member, and a first barrier layer. The sealing member seals the first semiconductor device, the second semiconductor device, the first conductive circuit pattern, and the second conductive circuit pattern. At least one of the first barrier layer and the sealing member includes a first stress relaxation portion. This configuration improves the reliability of the power semiconductor module.

A power semiconductor module includes an insulating substrate, a first conductive circuit pattern, a second conductive circuit pattern, a first semiconductor device, a second semiconductor device, a sealing member, and a first barrier layer. The sealing member seals the first semiconductor device, the second semiconductor device, the first conductive circuit pattern, and the second conductive circuit pattern. At least one of the first barrier layer and the sealing member includes a first stress relaxation portion. This configuration improves the reliability of the power semiconductor module.

A semiconductor apparatus is provided, including: a housing; a heat-dissipation substrate; a first semiconductor chip provided on the heat-dissipation substrate; a temperature detecting unit provided on the housing; a first thermoelectric member electrically connecting the first semiconductor chip and the temperature detecting unit; and a second thermoelectric member electrically connecting the first semiconductor chip and the temperature detecting unit, the second thermoelectric member being made of a different material than the first thermoelectric member. The thermal conductivity of the heat-dissipation substrate is higher than the thermal conductivity of the housing.

A semiconductor apparatus is provided, including: a housing; a heat-dissipation substrate; a first semiconductor chip provided on the heat-dissipation substrate; a temperature detecting unit provided on the housing; a first thermoelectric member electrically connecting the first semiconductor chip and the temperature detecting unit; and a second thermoelectric member electrically connecting the first semiconductor chip and the temperature detecting unit, the second thermoelectric member being made of a different material than the first thermoelectric member. The thermal conductivity of the heat-dissipation substrate is higher than the thermal conductivity of the housing.

A power-electronic metal-ceramic module (10) comprising a metal-ceramic substrate (12) made of a ceramic carrier (14) having a metal top and bottom ply (16, 18), which is joined on or in the metal top ply (16) and/or the metal bottom ply (18) with a metal layer (16, 18, 22, 23) forming a frame (24) for accommodating at least one electronic component (30) and at least one electronic component (30) accommodated in the frame (24).

A power-electronic metal-ceramic module (10) comprising a metal-ceramic substrate (12) made of a ceramic carrier (14) having a metal top and bottom ply (16, 18), which is joined on or in the metal top ply (16) and/or the metal bottom ply (18) with a metal layer (16, 18, 22, 23) forming a frame (24) for accommodating at least one electronic component (30) and at least one electronic component (30) accommodated in the frame (24).