Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

A semiconductor package includes a semiconductor chip and a polydimethylsiloxane (PDMS) layer that is provided on the semiconductor chip and of which upper surface is exposed to the outside. Since the semiconductor package may include the PDMS layer, heat emitting performance of the semiconductor package in a vacuum state may improve.

Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

An electronic device includes a printed circuit board (PCB) that supports an integrated circuit (IC) chip. The device also includes a lid over the IC chip. A thermal interface material (TIM) is configured to transfer thermal energy from the IC chip to the lid. A heat spreader forms a cavity in communication with the lid. The heat spreader is at least partially filled with a liquid that is configured to change phases during operation of the IC chip.

In one example, a semiconductor device, comprises a substrate having a top side and a conductor on the top side of the substrate, an electronic device on the top side of the substrate connected to the conductor on the top side of the substrate via an internal interconnect, a lid covering a top side of the electronic device, and a thermal material between the top side of the electronic device and the lid, wherein the lid has a through-hole. Other examples and related methods are also disclosed herein.

A package for housing an electronic component includes: a base portion including a first surface including a recessed portion in which an electronic component is mounted and also including a second surface located on an opposite side to the first surface; an external connection conductor located on the second surface; internal wiring located inside the base portion; first wiring located on the second surface and connected to the internal wiring; and second wiring located between the first wiring and the external connection conductor and connected to the external connection conductor, in which the first wiring and the second wiring are covered with an insulating layer.

A molded carrier is formed by a unitary body made of a laser direct structuring (LDS) material and includes a blind opening with a bottom surface. The unitary body includes: a floor body portion defining a back side and the bottom surface of the blind opening and an outer peripheral wall body portion defining a sidewall surface of the blind opening. LDS activation followed by electro-plating is used to produce: a die attach pad and bonding pad at the bottom surface; land grid array (LGA) pads at the back side; and vias extending through the floor body portion to make electrical connections between the die attach pad and one LGA pad and between the bonding pad and another LGA pad. An integrated circuit chip is mounted to the die attach pad and wire bonded to the bonding pad. A wafer-scale manufacturing process is used to form the molded carrier.

A stem for a semiconductor package, includes a plate, a frame, positioned on an outer periphery of the plate in a plan view, and bonded to the plate, and a lead terminal held in a state insulated from the plate and the frame. The plate protrudes from a top surface and a bottom surface of the frame, and a protruding amount of the plate from the top surface and a protruding amount of the plate from the bottom surface are the same.

The present invention relates to a millimeter wave radar component package, comprising: a box cover, having a metal layer arranged on inner surface of the box cover, the metal layer facing a channel of a box body, wherein a cavity is formed between the box cover and the box body; and the box body, comprising: a first insulator, connected with the box cover, wherein in the first insulator a channel is opened, and one end of the channel corresponds with the position of antenna and the other end is connected with the cavity; one or more chips, arranged on a second insulator in a flip manner and covered by the first insulator; the second insulator, arranged between the first insulator and a third insulator; the third insulator; and the antenna and conductive lines, arranged in the third insulator and connected with pads of the one or more chips through the second insulator, wherein the conductive lines are exposed from the third insulator for electrical contact. The present invention further relates to a method for manufacturing the package.