A semiconductor device, including a substrate having a mounting area on a front surface thereof, a semiconductor chip disposed in the mounting area, and an exterior member having a bottom surface bonded to the front surface of the substrate, the exterior member continuously surrounding the mounting area in a loop shape in a plan view of the semiconductor device, to thereby enclose a housing space, the mounting area being in the housing space. The semiconductor device further includes a sealing material sealing the housing space.

The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Semiconductor packages and a methods for manufacturing a semiconductor package are provided. The method includes providing a package including a substrate, a semiconductor chip provided on the substrate, and a molding layer provided on the substrate and covering the semiconductor chip, the substrate including a ground pattern exposed at one surface of the substrate; and applying a solution including metal particles and a conductive carbon material onto the molding layer to form a shielding layer covering the molding layer. The shielding layer includes the metal particles and the conductive carbon material connected to at least one of the metal particles. The shielding layer extends onto the one surface of the substrate and is electrically connected to the ground pattern.

A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles.

A heat-dissipating semiconductor package includes a substrate, a chip, a first encapsulation body, a second encapsulation body and a heat sink. The substrate has an inner surface. The chip is disposed on the inner surface of the substrate. The first encapsulation body is formed on the inner surface of the substrate and encapsulates the chip. The second encapsulation body is formed on the first encapsulation body and a periphery area of the inner surface to encapsulate sidewalls and a top surface of the first encapsulation body and cover the periphery area of the inner surface. Wherein, the Young's modulus of the second encapsulation body is less than the Young's modulus of the first encapsulation body. The heat sink is attached to the second encapsulation body. Thereby, the design of the heat-dissipating semiconductor package utilizes multiple encapsulation bodies to reduce the package warpage after installing the heat sink.

A resin composition of the present invention is a resin composition containing a bismaleimide compound (A) containing a constituent unit represented by the following formula (1), and maleimide groups at both ends of the molecular chain, at least one resin or compound (B) selected from the group consisting of a maleimide compound other than the bismaleimide compound (A), a cyanate compound, a benzoxazine compound, an epoxy resin, a carbodiimide compound, and a compound having an ethylenically unsaturated group, and a photo initiator (C): ##STR00001##
wherein R.sub.1 represents a linear or branched alkylene group having 1 to 16 carbon atoms, or a linear or branched alkenylene group having 2 to 16 carbon atoms; R.sub.2 represents a linear or branched alkylene group having 1 to 16 carbon atoms, or a linear or branched alkenylene group having 2 to 16 carbon atoms; each R.sub.3 independently represents a hydrogen atom, a linear or branched alkyl group having 1 to 16 carbon atoms, or a linear or branched alkenyl group having 2 to 16 carbon atoms; and each n independently represents an integer of 1 to 10.

Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.

A semiconductor device, including a semiconductor element; a case having a frame portion, which has an inner periphery that surrounds a housing space for accommodating the semiconductor element; and a lid covering the housing space. The inner periphery of the frame portion has a stepped portion formed thereon, the stepped portion including a step supporting surface positioned at a level lower than a front surface of the frame portion and being approximately parallel to the front surface of the frame portion. The lid has a lateral surface surrounding the lid, and a front surface and a bottom surface approximately parallel to the step supporting surface. The lid has a reservoir formed in the front surface thereof and extending from the lateral surface, the reservoir having a reservoir surface positioned at a level lower than the front surface of the lid.

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.