Disclosed is a semiconductor package comprising a semiconductor chip, a redistribution pattern on a bottom surface of the semiconductor chip and coupled to the semiconductor chip, a protection layer that covers a bottom surface of the redistribution pattern, a conductive pattern on a bottom surface of the protection layer and coupled to the redistribution pattern, a buffer pattern in contact with a bottom surface of a first part of the conductive pattern and with the bottom surface of the protection layer, and an under bump pattern on a bottom surface of the second part of the conductive pattern and covering a bottom surface and a side surface of the buffer pattern. The under bump pattern is coupled to the second part of the conductive pattern.

Flexible modules and methods of manufacture are described. In an embodiment, a flexible module includes a flex board formed in which a passivation layer is applied in liquid form in a panel level process, followed by exposure and development. An electronic component is then mounted onto the flex board and encapsulated in a molding compound that is directly on a top surface of the passivation layer.

A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

The present invention proposes a carrier substrate (1) for electrical components (13), the carrier substrate (1) having a component side (4) and a cooling side (5) which is opposite the component side (4) and has a cooling structure (30), the carrier substrate (1) comprising a primary layer (10) which faces the component side (4) and is produced from ceramic for electrical insulation, and a secondary layer (20) which faces the cooling side (5) for stiffening the carrier substrate (1), characterized in that a metallic intermediate layer (15) is arranged between the primary layer (10) and the secondary layer (20) for heat transfer from the component side (4) to the cooling side (5), the metallic intermediate layer (15) being thicker than the primary layer (10) and/or the secondary layer (20).

A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.

A device includes a redistribution layer (RDL) substrate. The device also includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate, opposite the first surface of the RDL substrate.

A semiconductor device includes a base having a first surface on which the semiconductor element is mounted and a second surface opposite to the first surface, a first edge portion having a step from the first surface toward the second surface in a first region of a peripheral edge of the base, a first terminal that is arranged at a position facing the first edge portion when viewed from a thickness direction of the base, a conductive member for electrically connecting the semiconductor element and the first terminal to each other, and a resin material for sealing a part of the base, the semiconductor element, and a part of the first terminal.

A semiconductor device has a substrate and first and second electrical component disposed over the substrate. A first metal bar is disposed over the substrate between the first electrical component and second electrical component. The first metal bar is formed by disposing a mask over a carrier. An opening is formed in the mask and a metal layer is sputtered over the mask. The mask is removed to leave the metal layer within the opening as the first metal bar. The first metal bar can be stored in a tape-and-reel.

A semiconductor package structure and a method for preparing the same are provided. The semiconductor package structure includes: a substrate; a first semiconductor chip located on the substrate, the first semiconductor chip having a first surface that is bare and the first surface having a silicon-containing surface; second semiconductor chip structures located on the first surface of the first semiconductor chip, the second semiconductor chip structures having second surfaces opposite to the first surface; a first package compound structure having a joint surface, the joint surface covering at least the first surface of the first semiconductor chip and the second surfaces of the second semiconductor chip structures. The joint surface has a silicon-containing surface.