Embedded die packaging for semiconductor devices and methods of fabrication wherein conductive vias are provided to interconnect contact areas on the die and package interconnect areas. Before embedding, a protective masking layer is provided selectively on regions of the electrical contact areas where vias are to be formed by laser drilling. The material of the protective masking layer is selected to protect against over-drilling and/or to control absorption properties of surface of the pad metal to reduce absorption of laser energy during laser drilling of micro-vias, thereby mitigating physical damage, overheating or other potential damage to the semiconductor device. The masking layer may be resistant to surface treatment of other regions of the electrical contact areas, e.g. to increase surface roughness to promote adhesion of package dielectric.

An electronic package, in which a heat dissipation structure is disposed on a carrier structure to form a packaging space for electronic components to be accommodated in the packaging space, and the electronic components are completely encapsulated by a heat dissipation material to prevent the electronic components exposing from the heat dissipation material so as to improve the heat dissipation effect.

Embodiments disclose a package structure and a fabricating method. The package structure includes: a semiconductor chip; a first non-conductive layer covering a front surface of the semiconductor chip and part of a side wall of the semiconductor chip; a second non-conductive layer positioned on an upper surface of the first non-conductive layer and covering at least part of a side wall of the first non-conductive layer, wherein a melt viscosity of the first non-conductive layer is greater than a melt viscosity of the second non-conductive layer; a substrate; and a solder mask layer positioned on a surface of the substrate, where a first opening is provided in the solder mask layer. The semiconductor chip is flip-chip bonded on the substrate, a surface of the second non-conductive layer away from the first non-conductive layer and a surface of the solder mask layer away from the substrate are bonding surfaces.

A semiconductor package includes an antenna structure including an antenna member configured to transmit and receive a signal through the first surface in the dielectric layer, a connection via extending from the antenna member toward the second surface, and a ground member spaced apart from the connection via; a frame surrounding the side surface of the antenna structure; a first encapsulant covering at least a portion of the antenna structure and the frame; a redistribution structure on the second surface and including an insulating layer in contact with the antenna structure and the frame, and a redistribution conductor configured to be electrically connected to the ground member and the connection via in the insulating layer; a first semiconductor chip on the redistribution structure and electrically connected to the antenna member through the redistribution conductor; a second encapsulant encapsulating the first semiconductor chip on the redistribution structure; and a shielding layer surrounding a surface of the second encapsulant.

Electrical components may have plastic packages. Contacts may be formed on exterior surfaces of the plastic packages. A plastic package for an electrical component may have an elongated shape that extends along a longitudinal axis. A first groove may run parallel to the longitudinal axis on a lower surface of the plastic package. A second groove may run perpendicular to the first groove on an opposing upper surface of the plastic package. The electrical components may be coupled to fibers in a fabric such as a woven fabric. A first solder connection may be formed between the first groove and a first fiber such as a weft fiber. A second solder connection may be formed between the second groove and a second fiber such as a warp fiber.

In one embodiment, methods for making semiconductor devices are disclosed.

A semiconductor device package includes a substrate, a first encapsulant and a second encapsulant. The substrate has an optical region and a surface-mount technology (SMT) device region. The first encapsulant includes a first portion disposed on the optical region and covers the optical region and a second portion disposed on the SMT device region and covers the SMT device region. The second encapsulant is disposed on the substrate and covers at least a portion of the second portion of the first encapsulant and a portion of the first portion of the first encapsulant.

A semiconductor device package and a method for manufacturing the same is provided. The semiconductor device package includes a semiconductor die having an electronic component integrated thereon and having a die terminal that is electrically connected to the electronic component, a stress relief substrate fixedly and electrically connected to the die terminal, and a clip lead. The substrate is configured to provide an electrical short between the clip lead and the die terminal. The stress relief substrate may form an interface between the clip lead and the semiconductor die and can thereby reduce stress exerted on the semiconductor die by the clip lead.

The disclosure provides a semiconductor package substrate made from non-metallic material having a first top surface, a second bottom surface opposite from the first surface, and at least one side surface, the substrate includes at least two pads positioned on the first surface and suitable for receiving an electronic element, an encapsulant material layer covering the first surface, at least two terminals positioned on the second surface and electrically connected to the pads, and a portion of at least one of the two terminals is exposed at the at least one side surface and structured as a wettable flank.

In general aspect, a module can include a substrate having a semiconductor circuit implemented thereon, and a negative power supply terminal electrically coupled with the semiconductor circuit via the substrate. The negative power supply terminal includes a connection tab arranged in a first plane. The module also includes a first positive power supply terminal electrically and a second positive power supply terminal that are coupled with the semiconductor circuit via the substrate. The first positive power supply terminal being laterally disposed from the negative power supply terminal, and including a connection tab arranged in the first plane. The second positive power supply terminal is laterally disposed from the negative power supply terminal and arranged in the first plane, such that the negative power supply terminal is disposed between the first positive power supply terminal and the second positive power supply terminal.