A semiconductor assembly includes a first die and a second die. The semiconductor assembly also includes a film on die (FOD) layer configured to attach the first die to the second die. The FOD layer is disposed on a first surface of the first die. The FOD layer includes a first portion comprising a first die attach film (DAF) disposed on an inner region of the first surface. The FOD layer also includes a second portion that includes a second DAF disposed on a peripheral region of the first surface surrounding the inner region. The second DAF includes a different material than the first DAF.

A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle θ is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<θ<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.

A processor substrate includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material and which exceeds a voltage limit of the processor substrate to a voltage that is below the voltage limit of the processor substrate. An electronic system that includes the processor substrate is also described.

A semiconductor package structure is provided. The semiconductor package structure includes an electronic component, and an inductance component. The protection layer encapsulates the electronic component and has a top surface and a bottom surface. The top surface and the bottom surface collectively define a space to accommodate the electronic component. The inductance component outflanks the space from the top surface and the bottom surface of the protection layer.

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

This invention provides a fan-out semiconductor package, the fan-out semiconductor package includes a frame including one or more insulating layers and having a penetration portion, a semiconductor chip disposed in the penetration portion of the frame and having a connection pad, a connection structure disposed on a lower side of the frame and the semiconductor chip and including a redistribution layer, a first encapsulant covering a back surface of the semiconductor chip and a first region of a top surface of an uppermost insulating layer among the one or more insulating layers of the frame and extending between a sidewall of the penetration portion and a side surface of the semiconductor chip, and a second encapsulant covering a second region of the top surface of the uppermost insulating layer among the one or more insulating layers of the frame and being in contact with a side surface of the first encapsulant on the frame.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar over a first portion of the first chip structure and over a second portion of the second chip structure. A width of the anti-warpage bar overlapping the second portion of the second chip structure is greater than a width of the anti-warpage bar overlapping the first portion of the first chip structure.

A semiconductor chip stack includes first and second semiconductor chips. The first chip includes a first semiconductor substrate having an active surface and an inactive surface, a first insulating layer formed on the inactive surface, and first pads formed in the first insulating layer. The second semiconductor chip includes a second semiconductor substrate having an active surface and an inactive surface, a second insulating layer formed on the active surface, second pads formed in the second insulating layer, a polymer layer formed on the second insulating layer, UBM patterns buried in the polymer layer; and buried solders formed on the UBM patterns, respectively, and buried in the polymer layer. A lower surface of the buried solders is coplanar with that of the polymer layer, the buried solders contact the first pads, respectively, at a contact surface, and a cross-sectional area of the buried solders is greatest on the contact surface.

A package structure includes a base material, at least one electronic device, at least one encapsulant and a plurality of dummy pillars. The electronic device is electrically connected to the base material. The encapsulant covers the electronic device. The dummy pillars are embedded in the encapsulant. At least two of the dummy pillars have different heights.

A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.