A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.

Structures and formation methods of a chip package structure are provided. The chip package structure includes a semiconductor die bonded over an interposer substrate. The chip package structure also includes a warpage release layer structure. The warpage release layer structure includes an organic material layer and an overlying high coefficient of thermal expansion (CTE) material layer with a CTE that is substantially equal to or greater than 9 ppm/° C. The organic material layer is in direct contact with the upper surface of the semiconductor die, and the overlying high CTE material layer covers the upper surface of the semiconductor die.

The present application provides a method for manufacturing a packaged chip and a packaged chip, a method for manufacturing a rewired packaged chip and a rewired packaged chip. In the present application, a dielectric layer that covers the surface of the chip and the conductive surface of the pads does not need to be partially removed by etching, the airtightness of the package chip may be improved to avoid the oxidation of the pads by air contact, and the pads are avoided from being etched by an etching process, such that the surface of the chip may be protected from being corroded by etching solution, which may result in short circuit.

A semiconductor package may include a redistribution substrate including first and second surfaces opposite each other, a first semiconductor chip on the first surface, a first molding portion on a side surface of the first semiconductor chip, a second semiconductor chip between the first semiconductor chip and the redistribution substrate, a second molding portion between the redistribution substrate and the first molding portion and on a side surface of the second semiconductor chip, bump patterns between the second semiconductor chip and the redistribution substrate, and a mold via penetrating the second molding portion and electrically connecting the first semiconductor chip to the redistribution substrate. The redistribution substrate may include first and second redistribution patterns sequentially in an insulating layer. The mold via may contact the second redistribution pattern, and the bump patterns may contact the first redistribution pattern.

Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

An electronic device module includes: a substrate; a sealing portion disposed on the substrate; at least one electronic device mounted on the substrate and embedded in the sealing portion; and a roof wiring at least partially disposed on a surface of the sealing portion and electrically connecting the substrate to the at least one electronic device or electrically connecting electronic devices, among the at least one electronic device, to each other. The roof wiring includes: a surface wiring disposed on one surface of the sealing portion; and at least one post wiring connecting the surface wiring to the substrate or to the at least one electronic device, and wherein at least a portion of a circumferential surface of the at least one post wiring is bonded to the surface wiring.

An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.