A semiconductor module includes: a chip carrier having a first side and a second, opposite side; a semiconductor chip arranged on the first side of the chip carrier; an encapsulation body that encapsulates the semiconductor chip; and at least two external contacts made of a metal or an alloy and arranged next to each other, which are electrically and mechanically connected to the first side of the first chip carrier and protrude laterally out of the encapsulation body. At least one of the external contacts has at least one wing arranged within the encapsulation body and located opposite the other external contact. The wing includes one or more cutouts that are filled with the encapsulation material of the encapsulation body.

There is provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where connection sections used for the connection to semiconductor elements are arranged. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have first surface sections on the side where the connection sections are arranged and second surface sections formed, on the side where the connection sections are not arranged, such that the peeling strength to the sealing resins is lower than that of the first surface sections.

There is provided a technique that includes: a lead having a main surface facing in a thickness direction; a semiconductor element mounted over the main surface; and a sealing resin that is in contact with the main surface and covers the semiconductor element, wherein the lead is formed with a plurality of grooves that are recessed from the main surface and are located apart from each other, and wherein the plurality of grooves are located away from a peripheral edge of the main surface.

An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.

A semiconductor device includes a semiconductor element, a sealing member, and a first conductive plate. The semiconductor element includes a first electrode. The sealing member seals the semiconductor element. The first conductive plate includes a first surface facing the first electrode inside the sealing member. The first surface of the first conductive plate includes a mounting region, a roughened region and a non-roughened region. The first electrode is joined to the mounting region. The roughened region is located around the mounting region. The non-roughened region is located between the roughened region and an outer peripheral edge of the first surface. Surface roughness of the roughened region is larger than surface roughness of the non-roughened region.

A semiconductor die is disclosed. The semiconductor die includes a semiconductor body, a metallization over part of the semiconductor body and including a noble metal at a top surface of the metallization, a bondwire having a foot bonded to the top surface of the metallization, and a sealing material covering the foot of the bondwire, the top surface of the metallization, and one or more areas outside the top surface of the metallization where oxide and/or hydroxide-groups would be present if exposed to air. The sealing material adheres to the foot of the bondwire and the one or more areas outside the top surface of the metallization where the oxide and/or hydroxide-groups would be present if exposed to air.

A semiconductor device includes a power module, a circuit package, and a joint portion joining the power module and the circuit package. The circuit package includes a semiconductor element, a wiring layer electrically connected with the semiconductor element, a heat conductive member, and a second mold resin portion sealing the semiconductor element and the heat conductive member. The wiring layer includes a connecting portion connected with the heat conductive member. One of the connecting portion or the heat conductive member is joined with a signal wire in the power module via the joint portion. The heat conductive member penetrates the second mold resin portion in a thickness direction of the semiconductor element. The heat conductive member and the connecting portion are arranged in a straight line in the thickness direction of the semiconductor element.

An electronic device includes a support member and a mount member mounting on the support member. The support member and the mount member are sealed by a resin member. The support member includes a surface having a laser irradiation mark. The mount member includes a surface having a rough portion with an accumulation of material of the support member.

In one general aspect, a semiconductor device package can include a die attach paddle having a first surface and a second surface that is opposite the first surface. The package can also include a semiconductor die coupled with the first surface of the die attach paddle. The package can further include a direct-bonded-metal (DBM) substrate. The DBM substrate can include a ceramic layer having a first surface and a second surface that is opposite the first surface; a first metal layer disposed on the first surface of the ceramic layer and coupled with the second surface of the die attach paddle; and a second metal layer disposed on the second surface of the ceramic layer. The second metal layer can be exposed external to the semiconductor device package. The second metal layer can be electrically isolated from the first metal layer by the ceramic layer.

The sensor semiconductor package (100) comprises a die pad (101), external connection terminals (103), semiconductor chip 105 and sealing member. The semiconductor chip (105) is located on a top surface of the die pad (101) and is electrically connected with the external connection terminals (103) and the die pad (101). The sealing member covers the die pad (101), the external connection terminals (103) and the semiconductor chip (105) and exposes an outer terminal (115) of each of the external connection terminals (103) and an outer contact surface (117) of the die pad (101). The outer contact surface (117) of the die pad (101) forms an electrode (117) of the sensor semiconductor package (100). The article comprises the sensor semiconductor package (100). The method manufactures the sensor semiconductor package (100) and the article.