The present disclosure relates to a package substrate comprising: a substrate having opposing first surface and second surface; at least one vent hole extending through the first surface and the second surface of the substrate, the vent hole comprising at least a long-strip hole.

A semiconductor device of embodiments includes: a die pad including a first region and a second region surrounding the first region and thinner than the first region; a semiconductor chip including an upper electrode, a lower electrode, and a silicon carbide layer between the upper electrode and the lower electrode and provided on an inner side rather than the second region on a surface of the die pad; and a connection layer for connecting the lower electrode to the surface.

A foil package includes a first foil substrate with a first and a second main surface, a second foil substrate with a first and a second main surface, wherein its first main surface is arranged facing the second main surface of the first foil substrate. The foil package includes at least one electronic device arranged between the first foil substrate and the second foil substrate and a first electrically conductive layer structure structured into a plurality of first partial areas arranged on the second main surface of the first foil substrate. The plurality of partial areas incompletely cover the second main surface of the first foil substrate. The at least one electronic device includes a terminal side and a side opposite to the terminal side.

A semiconductor device includes: a resin layer having a resin main surface; a mounting wiring layer arranged on the resin main surface, and having a mounting wiring main surface facing the same side as the resin main surface and a mounting wiring back surface facing the side of the resin main surface; a semiconductor element including an element wiring layer which is mounted on the mounting wiring main surface, has an element wiring main surface facing the side of the resin layer, and is connected to the mounting wiring layer; and a sealing resin which seals the mounting wiring layer and the semiconductor element, wherein the mounting wiring main surface and the element wiring main surface are rough surfaces having a larger surface roughness than the mounting wiring back surface.

A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.

A semiconductor module is provided with: a case having a frame that surrounds a substrate and a terminal block formed extending inward from an inner wall surface of the frame; a terminal having one end extending outward from the frame, and another end extending inward from the frame and being secured to a top face of the terminal block; a wiring member that electrically connects the terminal and a semiconductor element on the substrate; and an encapsulating resin that encapsulates the other end of the terminal, the wiring member, and the semiconductor element inside the case. A hole is formed in the top face of the terminal block. The hole is filled with the encapsulating resin, and is positioned closer to the inner wall surface of the frame than a bonding part between the terminal and the wiring member.

A semiconductor package including a redistribution substrate having lower and upper surfaces, the redistribution substrate including a pad on the lower surface, the pad having a first surface and a second surface, and a redistribution layer electrically connected to the pad; a semiconductor chip on the upper surface of the redistribution substrate and electrically connected to the redistribution layer; an encapsulant encapsulating at least a portion of the semiconductor chip; and a protective layer on the lower surface of the redistribution substrate and having an opening exposing at least a portion of the first surface of the pad, wherein the portion of the first surface exposed through the opening includes a recess surface including regular depressions and protrusions and being depressed inwardly toward the second surface, and an edge surface including irregular depressions and protrusions and having a step difference with respect to the recess surface.

A chip packaging structure includes a miniature antenna, an radio frequency identification chip, and a packaging member, wherein the radio frequency identification chip is electrically connected to the miniature antenna, and the packaging member is adapted to encapsulate the miniature antenna and the radio frequency identification chip, and has a top surface, a bottom surface, and a plurality of side surfaces, wherein the top surface, the bottom surface, and the side surfaces substantially form a hexahedron.

An integrated circuit (IC) package includes a package substrate, a first die over the package substrate, a stack of a first material and a second material over the first die, where the first material is between the first die and the second material and the second material includes an organic passivation material, interconnect structures including vias on the first die and extending through the first and second materials and conductive bumps on the second material, and a second die over the first die and connected to the first die via the interconnect structures, where a taper angle between an inner portion of a side wall of one of the vias and a plane parallel to a bottom opening of the one of the vias is less than or equal to 90 degrees.

A semiconductor device according to the present embodiment comprises a semiconductor chip comprising a first face and a second face on an opposite side to the first face, and comprising a first electrode in the first face. A first metallic member comprises a first opposed face facing the first electrode and being larger in a profile than the first electrode, the first metallic member comprising a first protruded portion protruded from the first opposed face toward the first electrode and electrically connected to the first electrode. An insulating member coats the semiconductor chip and the first metallic member.