An integrated circuit package includes a semiconductor die having a first surface and a second surface. The first surface is attached to a top surface of a die attach pad, and the second surface has a sensing area thereon. A mold compound covers or encapsulates at least a portion of the die attach pad and the semiconductor die. A channel is formed in a top portion of the mold compound. The channel extends from a first side of the mold compound to a second side of the mold compound. A cavity is formed between the channel and the sensing area so that the sensing area is exposed to the environment.

A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

A semiconductor device package includes a substrate, a first molding compound and antenna layer. The substrate has a first surface and a second surface opposite to the first surface. The first molding compound is disposed on the first surface of the substrate. The antenna layer is disposed on the first molding compound. The substrate, the first molding compound and the antenna layer define a cavity.

A semiconductor element is mounted on a die pad, and electrode pads arranged at an outer circumference of a surface of the semiconductor element are electrically connected to leads by wires, respectively. The semiconductor element, the die pad, and the leads are covered with an encapsulating resin. The semiconductor element has an element region having a high sensitivity with respect to stress, and an element region having a relatively low sensitivity with respect to stress. A recessed portion is formed in a surface of the encapsulating resin at a position above the element region having a high sensitivity with respect to stress.

Techniques are described for forming a sealed cavity within a semiconductor wafer, where a conductor wafer includes a structure, such as a T-gate electrode or passive component, formed over a substrate. The sealed-cavity structure may be embedded into the wafer without interfering with any subsequent processes. That is, once the cavity is closed, any subsequent backend processes may continue as usual.

A chip-interconnect arrangement including a substrate having a cavity, a chip having at least one chip contact and one chip contact surface, the chip being arranged in the cavity, an interconnect having an interconnect surface, the interconnect being applied on a surface of the substrate, and an electrically conductive adhesion medium, which electrically connects the at least one chip contact to the interconnect, wherein the interconnect surface is planar.

A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.

A flexible foil-based package is disclosed which comprises at least one flexible foil substrate on which at least one electronic device is mounted in flip-chip mounting technology. The flexible foil substrate is bent so that a recess is created in which the electronic device is arranged. A casting compound is applied to cover the electronic device.

Packaged devices are provided for use inside an electronic system that provides access for molding compound or cables by using groove-like features on the bottom of a device package or on top of a substrate, and methods regarding the same. The groove-like features prevent voids in the encapsulant before and after packaging of the electronic system.

A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure, encapsulating the semiconductor chip, and including an opaque or translucent resin; a mark indicating identification information and carved in the encapsulant; and a passivation layer disposed on the encapsulant and including a transparent resin.