The aim of the invention is to effectively protect a flat adhesive compound from permeates originating from the surroundings as well as from permeates trapped during lamination, winding, stacking or other processing steps. For this purpose, the adhesive tape comprises at least the following layers in the indicated order: a first outer adhesive compound layer A, a layer B, which contains at least one inorganic getter material, and a second outer adhesive compound layer C. The invention also relates to the use of said adhesive tape as an encapsulation material.

Described is an apparatus which comprises: a die having a first side and a second side opposite to the first side; a die backside film (DBF) or die attach film (DAF) disposed over the first side of the die; and a fluorocarbon layer disposed over the DBF or DAF. Described is a method which comprises: applying a die backside film (DBF) over a first side of a die, wherein the die has a second side which metal bumps; and applying a plasma polymerization process to treat the DBF with a fluorocarbon plasma.

The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film for flip chip type semiconductor back surface including an adhesive layer and a protective layer laminated on the adhesive layer, in which the protective layer is constituted of a heat-resistant resin having a glass transition temperature of 200 C. or more or a metal.

A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.

A thermal management solution may be provided for a microelectronic system including a flexible integrated heat spreader, wherein the flexible integrated heat spreader may comprise a plurality of thermally conductive structures having a flexible thermally conductive film attached to and extending between each of the plurality of thermally conductive structures. The flexible integrated heat spreader may be incorporated into multi-chip package by providing a microelectronic substrate having a plurality of microelectronic devices attached thereto and by thermally contacting each of the plurality of thermally conductive structures of the flexible integrated heat spreader to its respective microelectronic device on the microelectronic substrate.

Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.

A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer.

A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.

A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects.

A thermal management solution may be provided for a microelectronic system including a flexible integrated heat spreader, wherein the flexible integrated heat spreader may comprise a plurality of thermally conductive structures having a flexible thermally conductive film attached to and extending between each of the plurality of thermally conductive structures. The flexible integrated heat spreader may be incorporated into multi-chip package by providing a microelectronic substrate having a plurality of microelectronic devices attached thereto and by thermally contacting each of the plurality of thermally conductive structures of the flexible integrated heat spreader to its respective microelectronic device on the microelectronic substrate.